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| author | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
| commit | dd157937466f3ee18b08712625eba84582a913f3 (patch) | |
| tree | 6a4eadb148a2c8141032b78d3c521d56c1f34910 /fpga/usrp2/top/E1x0/timing.ucf | |
| parent | a1f36ebf436fccbb6cc81bb5f32a790d444772c2 (diff) | |
| parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
| download | uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.gz uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.bz2 uhd-dd157937466f3ee18b08712625eba84582a913f3.zip | |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2/top/E1x0/timing.ucf')
| -rw-r--r-- | fpga/usrp2/top/E1x0/timing.ucf | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/E1x0/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; |