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author | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
commit | dd157937466f3ee18b08712625eba84582a913f3 (patch) | |
tree | 6a4eadb148a2c8141032b78d3c521d56c1f34910 /fpga/usrp2/top/E1x0/tb_u1e.v | |
parent | a1f36ebf436fccbb6cc81bb5f32a790d444772c2 (diff) | |
parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
download | uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.gz uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.bz2 uhd-dd157937466f3ee18b08712625eba84582a913f3.zip |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2/top/E1x0/tb_u1e.v')
-rw-r--r-- | fpga/usrp2/top/E1x0/tb_u1e.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v new file mode 100644 index 000000000..188190f04 --- /dev/null +++ b/fpga/usrp2/top/E1x0/tb_u1e.v @@ -0,0 +1,58 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e |