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| author | Josh Blum <josh@joshknows.com> | 2012-08-31 11:20:17 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-08-31 11:20:17 -0700 |
| commit | 667dcf0b98bb5a99654cf883fb97d2a549582cff (patch) | |
| tree | 7c845d7ac3f506c000ab495b1d62d976b816b5cd /fpga/usrp2/top/E1x0/Makefile.E110 | |
| parent | 05a06254a7f0149425bdda0e5544507bd35a671b (diff) | |
| parent | 36a7def9aa6cecaa6f3cbf9979544d6fd5848a08 (diff) | |
| download | uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.tar.gz uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.tar.bz2 uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.zip | |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/E1x0/Makefile.E110')
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile.E110 | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 index 89e51b523..e5be8d2fa 100644 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -5,7 +5,7 @@ ################################################## # Project Setup ################################################## -TOP_MODULE = u1e +TOP_MODULE = E1x0 BUILD_DIR = $(abspath build$(ISE)-E110) # set me in a custom makefile @@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u1e_core.v \ -u1e.v \ -u1e.ucf \ +../B100/u1plus_core.v \ +E1x0.v \ +E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |