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| author | Josh Blum <josh@joshknows.com> | 2012-07-17 12:33:40 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-17 12:33:40 -0700 |
| commit | 1b677b1cc46718ed9473700e2bb88666b70808f3 (patch) | |
| tree | 9aa45721cb5f7b92f56243527cd2fc912ed3f976 /fpga/usrp2/top/E1x0/Makefile.E110 | |
| parent | f3e7f66907bf2d77258ae38a6117927a46fe41a6 (diff) | |
| parent | 9ecbfeb8ee52b6a59b8757cb259b325cebd05199 (diff) | |
| download | uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.tar.gz uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.tar.bz2 uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/E1x0/Makefile.E110')
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile.E110 | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 index 89e51b523..e5be8d2fa 100644 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -5,7 +5,7 @@ ################################################## # Project Setup ################################################## -TOP_MODULE = u1e +TOP_MODULE = E1x0 BUILD_DIR = $(abspath build$(ISE)-E110) # set me in a custom makefile @@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u1e_core.v \ -u1e.v \ -u1e.ucf \ +../B100/u1plus_core.v \ +E1x0.v \ +E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |