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authorJosh Blum <josh@joshknows.com>2013-05-09 17:40:52 -0700
committerJosh Blum <josh@joshknows.com>2013-05-09 17:40:52 -0700
commit845dd30d8ba2113f86ff762e0c848fac9b171655 (patch)
tree8b94ce0d2a7853fe8cdd9449279c0b0830832560 /fpga/usrp2/top/B100
parentb0a4e2ad081cc55ad309d44b59583f0140f87608 (diff)
parent286f0d8d3830417cbf26ac494bb960b4ba735944 (diff)
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Merge branch 'fpga_master' into maint
Diffstat (limited to 'fpga/usrp2/top/B100')
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 302565101..9fe09c60e 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -71,7 +71,7 @@ module u1plus_core
localparam SR_GPIO = 224; // 5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd11, 16'd2}; //major, minor
+ localparam compat_num = {16'd11, 16'd3}; //major, minor
//assign run signals used for ATR logic
wire [NUM_RX_DSPS-1:0] run_rx_n;