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| author | Josh Blum <josh@joshknows.com> | 2011-08-31 18:29:34 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-31 18:29:34 -0700 |
| commit | d6d017aa58fd858a752ac43a6a6c24704758e444 (patch) | |
| tree | 6f4b3388754d00d149a14c97f4ce6764e5d9a60c /fpga/usrp2/top/B100 | |
| parent | 208885b6dc8a01a1d7095cff5b36c8451601259c (diff) | |
| parent | 4f04b93d23015a56b2a2d4e87541b24de36c9018 (diff) | |
| download | uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.tar.gz uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.tar.bz2 uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.zip | |
Merge branch 'fpga_master' into next
Diffstat (limited to 'fpga/usrp2/top/B100')
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 6a80eba76..b40083201 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -89,7 +89,7 @@ module u1plus_core .in(set_data),.out(),.changed(global_reset)); reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); - reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); + reset_sync reset_sync_gp(.clk(gpif_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// |