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authorJosh Blum <josh@joshknows.com>2011-08-15 18:55:57 -0700
committerJosh Blum <josh@joshknows.com>2011-08-15 18:55:57 -0700
commit06dc097530730621515863b40411581e1d3422b7 (patch)
treee0fab8d37bc75c16a079647eb2bf58fe072dddfb /fpga/usrp2/top/B100
parent26a75aca7c7408dbb9c34d68761b043434e1d13b (diff)
parentccafda72b4d1acf820be26e488bbfc530ca31c65 (diff)
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Merge branch 'fpga_patch_release' into patch_releaserelease_003_002_002
Diffstat (limited to 'fpga/usrp2/top/B100')
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 4683f653c..6a80eba76 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -142,7 +142,7 @@ module u1plus_core
// RX ADC Frontend, does IQ Balance, DC Offset, muxing
wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p
- wire run_rx, run_rx0, run_rx1;
+ wire run_rx0, run_rx1;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(wb_clk),.rst(wb_rst),
@@ -421,7 +421,7 @@ module u1plus_core
(.clk_i(wb_clk), .rst_i(wb_rst),
.adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
.we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
- .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
+ .run_rx(run_rx0 | run_rx1), .run_tx(run_tx), .ctrl_lines(atr_lines));
// /////////////////////////////////////////////////////////////////////////
// Readback mux 32 -- Slave #7