Removed copy of FPGA source files.

9 files changed, 0 insertions, 1039 deletions

diff --git a/fpga/usrp2/top/B100/.gitignore b/fpga/usrp2/top/B100/.gitignore
deleted file mode 100644
index 1b2211df0..000000000
--- a/fpga/usrp2/top/B100/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build*
diff --git a/fpga/usrp2/top/B100/B100.ucf b/fpga/usrp2/top/B100/B100.ucf
deleted file mode 100644
index 1c04c5d8d..000000000
--- a/fpga/usrp2/top/B100/B100.ucf
+++ /dev/null
@@ -1,204 +0,0 @@
-## Main Clock
-NET "CLK_FPGA_P"  LOC = "R7"  ;
-NET "CLK_FPGA_N"  LOC = "T7"  ;
-
-## I2C
-NET "SDA_FPGA"  LOC = "T13"  ;
-NET "SCL_FPGA"  LOC = "R13"  ;
-
-## CGEN
-NET "cgen_st_ld"  LOC = "M13"  ;
-NET "cgen_st_refmon"  LOC = "J14"  ;
-NET "cgen_st_status"  LOC = "P6"  ;
-NET "cgen_ref_sel"  LOC = "T2"  ;
-NET "cgen_sync_b"  LOC = "H15"  ;
-
-## FPGA Config
-#NET "fpga_cfg_din"  LOC = "T14"  ;
-#NET "fpga_cfg_cclk"  LOC = "R14"  ;
-#NET "fpga_cfg_init_b"  LOC = "T12"  ;
-
-## MISC
-#NET "mystery_bus<1>"  LOC = "C4"  ;
-#NET "mystery_bus<0>"  LOC = "E7"  ;
-NET "reset_n"  LOC = "D5"  ;
-NET "PPS_IN"  LOC = "M14"  ;
-NET "reset_codec"  LOC = "B14"  ;
-
-## recycles fpga_cfg_cclk for reset from fw
-NET "ext_reset"  LOC = "R14"  ;
-
-## GPIF
-NET "GPIF_D<15>"  LOC = "P7"  ;
-NET "GPIF_D<14>"  LOC = "N8"  ;
-NET "GPIF_D<13>"  LOC = "T5"  ;
-NET "GPIF_D<12>"  LOC = "T6"  ;
-NET "GPIF_D<11>"  LOC = "N6"  ;
-NET "GPIF_D<10>"  LOC = "P5"  ;
-NET "GPIF_D<9>"  LOC = "R3"  ;
-NET "GPIF_D<8>"  LOC = "T3"  ;
-NET "GPIF_D<7>"  LOC = "N12"  ;
-NET "GPIF_D<6>"  LOC = "P13"  ;
-NET "GPIF_D<5>"  LOC = "P11"  ;
-NET "GPIF_D<4>"  LOC = "R9"  ;
-NET "GPIF_D<3>"  LOC = "T9"  ;
-NET "GPIF_D<2>"  LOC = "N9"  ;
-NET "GPIF_D<1>"  LOC = "P9"  ;
-NET "GPIF_D<0>"  LOC = "P8"  ;
-
-##NET "GPIF_CTL<3>"  LOC = "N5"  ;
-NET "GPIF_CTL<3>"  LOC = "P12"  ;
-NET "GPIF_CTL<2>"  LOC = "M11"  ;
-NET "GPIF_CTL<1>"  LOC = "M9"  ;
-NET "GPIF_CTL<0>"  LOC = "M7"  ;
-
-##NET "GPIF_RDY<3>"  LOC = "N11"  ;
-##NET "GPIF_RDY<2>"  LOC = "T10"  ;
-NET "GPIF_SLWR"  LOC = "T4"  ;
-NET "GPIF_SLRD"  LOC = "R5"  ;
-
-##NET "GPIF_CS"  LOC = "P12"  ;
-NET "GPIF_SLOE"  LOC = "R11"  ;
-NET "GPIF_PKTEND"  LOC = "P10"  ;
-NET "GPIF_ADR<0>"  LOC = "T11"  ;
-NET "GPIF_ADR<1>"  LOC = "H16"  ;
-
-NET "IFCLK"  LOC = "T8"  ;
-
-## LEDs
-NET "debug_led<2>"  LOC = "R2"  ;
-NET "debug_led<1>"  LOC = "N4"  ;
-NET "debug_led<0>"  LOC = "P4"  ;
-
-## Debug bus
-NET "debug_clk<0>"  LOC = "K15"  ;
-NET "debug_clk<1>"  LOC = "K14"  ;
-NET "debug<0>"  LOC = "K16"  ;
-NET "debug<1>"  LOC = "J16"  ;
-NET "debug<2>"  LOC = "C16"  ;
-NET "debug<3>"  LOC = "C15"  ;
-NET "debug<4>"  LOC = "E13"  ;
-NET "debug<5>"  LOC = "D14"  ;
-NET "debug<6>"  LOC = "D16"  ;
-NET "debug<7>"  LOC = "D15"  ;
-NET "debug<8>"  LOC = "E14"  ;
-NET "debug<9>"  LOC = "F13"  ;
-NET "debug<10>"  LOC = "G13"  ;
-NET "debug<11>"  LOC = "F14"  ;
-NET "debug<12>"  LOC = "E16"  ;
-NET "debug<13>"  LOC = "F15"  ;
-NET "debug<14>"  LOC = "H13"  ;
-NET "debug<15>"  LOC = "G14"  ;
-NET "debug<16>"  LOC = "G16"  ;
-NET "debug<17>"  LOC = "F16"  ;
-NET "debug<18>"  LOC = "J12"  ;
-NET "debug<19>"  LOC = "J13"  ;
-NET "debug<20>"  LOC = "L14"  ;
-NET "debug<21>"  LOC = "L16"  ;
-NET "debug<22>"  LOC = "M15"  ;
-NET "debug<23>"  LOC = "M16"  ;
-NET "debug<24>"  LOC = "L13"  ;
-NET "debug<25>"  LOC = "K13"  ;
-NET "debug<26>"  LOC = "P16"  ;
-NET "debug<27>"  LOC = "N16"  ;
-NET "debug<28>"  LOC = "R15"  ;
-NET "debug<29>"  LOC = "P15"  ;
-NET "debug<30>"  LOC = "N13"  ;
-NET "debug<31>"  LOC = "N14"  ;
-
-## ADC
-NET "adc<11>"  LOC = "B15"  ;
-NET "adc<10>"  LOC = "A8"  ;
-NET "adc<9>"  LOC = "B8"  ;
-NET "adc<8>"  LOC = "C8"  ;
-NET "adc<7>"  LOC = "D8"  ;
-NET "adc<6>"  LOC = "C9"  ;
-NET "adc<5>"  LOC = "A9"  ;
-NET "adc<4>"  LOC = "C10"  ;
-NET "adc<3>"  LOC = "D9"  ;
-NET "adc<2>"  LOC = "A3"  ;
-NET "adc<1>"  LOC = "B3"  ;
-NET "adc<0>"  LOC = "A4"  ;
-NET "RXSYNC"  LOC = "D10"  ;
-
-## DAC
-NET "TXBLANK"  LOC = "K1"  ;
-NET "TXSYNC"  LOC = "J2"  ;
-NET "dac<0>"  LOC = "J1"  ;
-NET "dac<1>"  LOC = "H3"  ;
-NET "dac<2>"  LOC = "J3"  ;
-NET "dac<3>"  LOC = "G2"  ;
-NET "dac<4>"  LOC = "H1"  ;
-NET "dac<5>"  LOC = "N3"  ;
-NET "dac<6>"  LOC = "M4"  ;
-NET "dac<7>"  LOC = "R1"  ;
-NET "dac<8>"  LOC = "P2"  ;
-NET "dac<9>"  LOC = "P1"  ;
-NET "dac<10>"  LOC = "M1"  ;
-NET "dac<11>"  LOC = "N1"  ;
-NET "dac<12>"  LOC = "M3"  ;
-NET "dac<13>"  LOC = "L4"  ;
-
-## TX DB
-NET "io_tx<0>"  LOC = "K4"  ;
-NET "io_tx<1>"  LOC = "L3"  ;
-NET "io_tx<2>"  LOC = "L2"  ;
-NET "io_tx<3>"  LOC = "F1"  ;
-NET "io_tx<4>"  LOC = "F3"  ;
-NET "io_tx<5>"  LOC = "G3"  ;
-NET "io_tx<6>"  LOC = "E3"  ;
-NET "io_tx<7>"  LOC = "E2"  ;
-NET "io_tx<8>"  LOC = "E4"  ;
-NET "io_tx<9>"  LOC = "F4"  ;
-NET "io_tx<10>"  LOC = "D1"  ;
-NET "io_tx<11>"  LOC = "E1"  ;
-NET "io_tx<12>"  LOC = "D4"  ;
-NET "io_tx<13>"  LOC = "D3"  ;
-NET "io_tx<14>"  LOC = "C2"  ;
-NET "io_tx<15>"  LOC = "C1"  ;
-
-## RX DB
-NET "io_rx<0>"  LOC = "D7"  ;
-NET "io_rx<1>"  LOC = "C6"  ;
-NET "io_rx<2>"  LOC = "A6"  ;
-NET "io_rx<3>"  LOC = "B6"  ;
-NET "io_rx<4>"  LOC = "E9"  ;
-NET "io_rx<5>"  LOC = "A7"  ;
-NET "io_rx<6>"  LOC = "C7"  ;
-NET "io_rx<7>"  LOC = "B10"  ;
-NET "io_rx<8>"  LOC = "A10"  ;
-NET "io_rx<9>"  LOC = "C11"  ;
-NET "io_rx<10>"  LOC = "A11"  ;
-NET "io_rx<11>"  LOC = "D11"  ;
-NET "io_rx<12>"  LOC = "B12"  ;
-NET "io_rx<13>"  LOC = "A12"  ;
-NET "io_rx<14>"  LOC = "A14"  ;
-NET "io_rx<15>"  LOC = "A13"  ;
-
-## SPI
-#NET "SEN_AUX"  LOC = "C12"  ;
-#NET "SCLK_AUX"  LOC = "D12"  ;
-#NET "MISO_AUX"  LOC = "J5"  ;
-NET "SCLK_CODEC"  LOC = "K3"  ;
-NET "SEN_CODEC"  LOC = "D13"  ;
-NET "MOSI_CODEC"  LOC = "C13"  ;
-NET "MISO_CODEC"  LOC = "G4"  ;
-
-NET "MISO_RX_DB"  LOC = "E6"  ;
-NET "SEN_RX_DB"  LOC = "B4"  ;
-NET "MOSI_RX_DB"  LOC = "A5"  ;
-NET "SCLK_RX_DB"  LOC = "C5"  ;
-
-NET "MISO_TX_DB"  LOC = "J4"  ;
-NET "SEN_TX_DB"  LOC = "N2"  ;
-NET "MOSI_TX_DB"  LOC = "L1"  ;
-NET "SCLK_TX_DB"  LOC = "G1"  ;
-
-## Dedicated pins
-#NET "TMS"  LOC = "B2"  ;
-#NET "TDO"  LOC = "B16"  ;
-#NET "TDI"  LOC = "B1"  ;
-#NET "TCK"  LOC = "A15"  ;
-
-#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
-#NET "fpga_cfg_done"  LOC = "T15"  ;
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
deleted file mode 100644
index d26d0a0d0..000000000
--- a/fpga/usrp2/top/B100/B100.v
+++ /dev/null
@@ -1,218 +0,0 @@
-//
-// Copyright 2011-2012 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module B100
-  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-
-   // GPIF
-   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output GPIF_SLOE, 
-   output [1:0] GPIF_ADR, output GPIF_SLWR, output GPIF_SLRD, output GPIF_PKTEND,
-   input IFCLK,
-   
-   inout SDA_FPGA, inout SCL_FPGA, // I2C
-
-   output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,   // DB TX SPI
-   output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,   // DB TX SPI
-   output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC,   // AD9862 main SPI
-
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
-   
-   inout [15:0] io_tx, inout [15:0] io_rx,
-
-   output [13:0] dac, output TXSYNC, output TXBLANK,
-   input [11:0] adc, input RXSYNC,
-  
-   input PPS_IN,
-   input reset_n, output reset_codec,
-   input ext_reset
-   );
-
-   assign reset_codec = 1;  // Believed to be active low
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Clocking
-   wire  clk_fpga, clk_fpga_in, reset;
-   wire gpif_clk = IFCLK;
-   wire gpif_rst;
-   
-   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
-   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
-
-   BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
-   
-   reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset));
-   reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst));
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // SPI
-   wire  mosi, sclk, miso;
-   assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
-   assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
-		 (~SEN_CODEC & MISO_CODEC);
-
-   // /////////////////////////////////////////////////////////////////////////
-   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
-
-   assign TXBLANK = 0;
-   wire [13:0] tx_i, tx_q;
-
-   genvar i;
-   generate
-      for(i=0;i<14;i=i+1)
-	begin : gen_dacout
-	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   ODDR2_inst (.Q(dac[i]),      // 1-bit DDR output data
-		       .C0(clk_fpga),  // 1-bit clock input
-		       .C1(~clk_fpga), // 1-bit clock input
-		       .CE(1'b1),      // 1-bit clock enable input
-		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
-		       .D1(tx_q[i]),   // 1-bit data input (associated with C1)
-		       .R(1'b0),       // 1-bit reset input
-		       .S(1'b0));      // 1-bit set input
-	end // block: gen_dacout
-      endgenerate
-   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
-		.C0(clk_fpga),  // 1-bit clock input
-		.C1(~clk_fpga), // 1-bit clock input
-		.CE(1'b1),      // 1-bit clock enable input
-		.D0(1'b0),   // 1-bit data input (associated with C0)
-		.D1(1'b1),   // 1-bit data input (associated with C1)
-		.R(1'b0),       // 1-bit reset input
-		.S(1'b0));      // 1-bit set input
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX ADC -- handles deinterleaving
-
-   wire rxsync_0, rxsync_1;
-   reg [11:0] rx_i, rx_q;
-   wire [11:0] rx_a, rx_b;
-   
-   genvar      j;
-   generate
-      for(j=0;j<12;j=j+1)
-	begin : gen_adcin
-	   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-		   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-		   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   IDDR2_inst (.Q0(rx_a[j]),      // 1-bit output captured with C0 clock
-		       .Q1(rx_b[j]),      // 1-bit output captured with C1 clock
-		       .C0(clk_fpga),     // 1-bit clock input
-		       .C1(~clk_fpga),    // 1-bit clock input
-		       .CE(1'b1),         // 1-bit clock enable input
-		       .D(adc[j]),        // 1-bit DDR data input
-		       .R(1'b0),          // 1-bit reset input
-		       .S(1'b0));         // 1-bit set input
-	end // block: gen_adcin
-   endgenerate
-   
-   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-	   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-	   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   IDDR2_sync (.Q0(rxsync_0),      // 1-bit output captured with C0 clock
-	       .Q1(rxsync_1),      // 1-bit output captured with C1 clock
-	       .C0(clk_fpga),     // 1-bit clock input
-	       .C1(~clk_fpga),    // 1-bit clock input
-	       .CE(1'b1),         // 1-bit clock enable input
-	       .D(RXSYNC),        // 1-bit DDR data input
-	       .R(1'b0),          // 1-bit reset input
-	       .S(1'b0));         // 1-bit set input
-
-   always @(posedge clk_fpga)
-     if(rxsync_0)
-       begin
-	  rx_i <= ~rx_b;
-	  rx_q <= ~rx_a;
-       end
-     else
-       begin
-	  rx_i <= ~rx_a;
-	  rx_q <= ~rx_b;
-       end
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Main Core
-   wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
-   wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
-   wire dsp_rx_run, dsp_tx_run;
-   wire [7:0] sen8;
-   assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0];
-    wire [31:0] core_debug;
-
-   assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld};
-   wire cgen_sync;
-   assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
-
-   u1plus_core #(
-`ifdef NUM_RX_DSP
-        .NUM_RX_DSPS(`NUM_RX_DSP),
-`else
-        .NUM_RX_DSPS(1),
-`endif
-        .DSP_RX_XTRA_FIFOSIZE(11),
-        .DSP_TX_XTRA_FIFOSIZE(12),
-        .USE_PACKET_PADDER(1)
-    ) core(
-         .clk(clk_fpga), .reset(reset),
-         .debug(core_debug), .debug_clk(debug_clk),
-
-         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
-         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
-         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
-         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
-
-         .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
-         .clock_sync(cgen_sync),
-
-         .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
-         .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
-         .io_tx(io_tx), .io_rx(io_rx),
-         .tx_i(tx_i), .tx_q(tx_q),
-         .rx_i(rx_i), .rx_q(rx_q),
-         .pps_in(PPS_IN) );
-
-    // /////////////////////////////////////////////////////////////////////////
-    // Interface from host to/from GPIF
-    wire [31:0] gpif_debug;
-    slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D),
-         .gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD),
-         .pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR),
-
-         .fifo_clk(clk_fpga), .fifo_rst(reset),
-         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
-         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
-         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
-         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
-
-         .debug(gpif_debug));
-
-    //assign debug = gpif_debug;
-    assign debug = core_debug;
-
-endmodule // B100
diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile
deleted file mode 100644
index fdd507394..000000000
--- a/fpga/usrp2/top/B100/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright 2011 Ettus Research LLC
-#
-
-all: B100 B100_2RX
-	find -name "*.twr" | xargs grep constraint | grep met
-
-clean:
-	rm -rf build*
-
-B100:
-	make -f Makefile.$@ bin
-
-B100_2RX:
-	make -f Makefile.$@ bin
-
-.PHONY: all clean
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100
deleted file mode 100644
index 4687f2169..000000000
--- a/fpga/usrp2/top/B100/Makefile.B100
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-# Copyright 2008-2012 Ettus Research LLC
-#
-
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE := B100
-BUILD_DIR := build-B100/
-
-# set me in a custom makefile
-CUSTOM_SRCS =
-CUSTOM_DEFS =
-
-##################################################
-# Include other makefiles
-##################################################
-
-include ../Makefile.common
-include ../../fifo/Makefile.srcs
-include ../../control_lib/Makefile.srcs
-include ../../sdr_lib/Makefile.srcs
-include ../../serdes/Makefile.srcs
-include ../../simple_gemac/Makefile.srcs
-include ../../timing/Makefile.srcs
-include ../../opencores/Makefile.srcs
-include ../../vrt/Makefile.srcs
-include ../../udp/Makefile.srcs
-include ../../coregen/Makefile.srcs
-include ../../gpif/Makefile.srcs
-
-##################################################
-# Project Properties
-##################################################
-export PROJECT_PROPERTIES := \
-family "Spartan3A" \
-device XC3S1400A \
-package ft256 \
-speed -4 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE 
-
-##################################################
-# Sources
-##################################################
-TOP_SRCS = \
-B100.v \
-u1plus_core.v \
-B100.ucf \
-timing.ucf
-
-SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
-$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
-
-##################################################
-# Process Properties
-##################################################
-SYNTHESIZE_PROPERTIES = \
-"Number of Clock Buffers" 8 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto \
-"Verilog Macros" "$(CUSTOM_DEFS)"
-
-TRANSLATE_PROPERTIES = \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-MAP_PROPERTIES = \
-"Generate Detailed MAP Report" TRUE \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-PLACE_ROUTE_PROPERTIES = \
-"Place & Route Effort Level (Overall)" High 
-
-STATIC_TIMING_PROPERTIES = \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-GEN_PROG_FILE_PROPERTIES = \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/B100/Makefile.B100_2RX b/fpga/usrp2/top/B100/Makefile.B100_2RX
deleted file mode 100644
index ba535dfb0..000000000
--- a/fpga/usrp2/top/B100/Makefile.B100_2RX
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-# Copyright 2008-2012 Ettus Research LLC
-#
-
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE := B100
-BUILD_DIR := build-B100_2RX/
-
-# set me in a custom makefile
-CUSTOM_SRCS =
-CUSTOM_DEFS =
-
-##################################################
-# Include other makefiles
-##################################################
-
-include ../Makefile.common
-include ../../fifo/Makefile.srcs
-include ../../control_lib/Makefile.srcs
-include ../../sdr_lib/Makefile.srcs
-include ../../serdes/Makefile.srcs
-include ../../simple_gemac/Makefile.srcs
-include ../../timing/Makefile.srcs
-include ../../opencores/Makefile.srcs
-include ../../vrt/Makefile.srcs
-include ../../udp/Makefile.srcs
-include ../../coregen/Makefile.srcs
-include ../../gpif/Makefile.srcs
-
-##################################################
-# Project Properties
-##################################################
-export PROJECT_PROPERTIES := \
-family "Spartan3A" \
-device XC3S1400A \
-package ft256 \
-speed -4 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE 
-
-##################################################
-# Sources
-##################################################
-TOP_SRCS = \
-B100.v \
-u1plus_core.v \
-B100.ucf \
-timing.ucf
-
-SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
-$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
-$(GPIF_SRCS)
-
-##################################################
-# Process Properties
-##################################################
-SYNTHESIZE_PROPERTIES = \
-"Number of Clock Buffers" 8 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto \
-"Verilog Macros" "NUM_RX_DSP=2 DISABLE_TX_DSP=1 $(CUSTOM_DEFS)"
-
-TRANSLATE_PROPERTIES = \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-MAP_PROPERTIES = \
-"Generate Detailed MAP Report" TRUE \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-PLACE_ROUTE_PROPERTIES = \
-"Place & Route Effort Level (Overall)" High 
-
-STATIC_TIMING_PROPERTIES = \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-GEN_PROG_FILE_PROPERTIES = \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile
deleted file mode 100755
index 2192bfa94..000000000
--- a/fpga/usrp2/top/B100/core_compile
+++ /dev/null
@@ -1 +0,0 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
deleted file mode 100644
index 7b212a9a6..000000000
--- a/fpga/usrp2/top/B100/timing.ucf
+++ /dev/null
@@ -1,24 +0,0 @@
-NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
-TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
-
-NET "IFCLK" TNM_NET = "IFCLK";
-TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %;
-
-#constrain FX2 IO
-INST "GPIF_D<*>" TNM = gpif_net_in;
-INST "GPIF_CTL<*>" TNM = gpif_net_in;
-
-INST "GPIF_D<*>" TNM = gpif_net_out;
-INST "GPIF_ADR<*>" TNM = gpif_net_out;
-INST "GPIF_SLWR" TNM = gpif_net_out;
-INST "GPIF_SLOE" TNM = gpif_net_out;
-INST "GPIF_SLRD" TNM = gpif_net_out;
-INST "GPIF_PKTEND" TNM = gpif_net_out;
-
-TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING;
-TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;
-
-TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
-
-NET PPS_IN TIG;
-NET debug_led* TIG;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
deleted file mode 100644
index 7f137f0d1..000000000
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ /dev/null
@@ -1,362 +0,0 @@
-//
-// Copyright 2011-2013 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-
-module u1plus_core
-#(
-    parameter NUM_RX_DSPS = 2,
-    parameter CTRL_ACK_SID = 20,      //needed for reply
-
-    parameter DSP_TX_FIFOSIZE = 10,     //4K MTU
-    parameter DSP_RX_FIFOSIZE = 10,     //4K MTU
-
-    parameter DSP_RX_XTRA_FIFOSIZE = 11,
-    parameter DSP_TX_XTRA_FIFOSIZE = 11,
-
-    parameter USE_PACKET_PADDER = 0
-)
-  (input clk, input reset,
-   output [31:0] debug, output [1:0] debug_clk,
-
-   // Host Interface
-   input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy,
-   output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy,
-   input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy,
-   output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy,
-
-   output dsp_rx_run, output dsp_tx_run, output clock_sync,
-
-   inout db_sda, inout db_scl,
-   output sclk, output [7:0] sen, output mosi, input miso,
-
-   inout [15:0] io_tx, inout [15:0] io_rx,
-   output [13:0] tx_i, output [13:0] tx_q,
-   input [11:0] rx_i, input [11:0] rx_q,
-   input pps_in
-   );
-
-    localparam SR_MISC         = 0;      // 5
-    localparam SR_USER_REGS    = 5;      // 2
-    localparam SR_PADDER       = 10;     // 2
-
-    localparam SR_TX_CTRL      = 32;     // 6
-    localparam SR_TX_DSP       = 40;     // 5
-    localparam SR_TX_FE        = 48;     // 5
-
-    localparam SR_RX_CTRL0     = 96;      // 9
-    localparam SR_RX_DSP0      = 106;     // 7
-    localparam SR_RX_FE        = 114;     // 5
-
-    localparam SR_RX_CTRL1     = 128;     // 9
-    localparam SR_RX_DSP1      = 138;     // 7
-
-    localparam SR_TIME64       = 192;     // 6
-    localparam SR_SPI          = 208;     // 3
-    localparam SR_I2C          = 216;     // 1
-    localparam SR_GPIO         = 224;     // 5
-
-    //compatibility number -> increment when the fpga has been sufficiently altered
-    localparam compat_num = {16'd11, 16'd4}; //major, minor
-
-    //assign run signals used for ATR logic
-    wire [NUM_RX_DSPS-1:0] run_rx_n;
-    wire run_tx;
-    wire run_rx = |(run_rx_n);
-    assign dsp_rx_run = run_rx;
-    assign dsp_tx_run = run_tx;
-
-    //shared time core signals
-    wire [63:0] vita_time, vita_time_pps;
-
-    //shared settings bus signals
-    wire set_stb, set_stb_user;
-    wire [31:0] set_data, set_data_user;
-    wire [7:0] set_addr, set_addr_user;
-
-    //shared SPI core signals
-    wire [31:0] spi_readback;
-    wire spi_ready;
-
-    //shared I2C core signals
-    wire [31:0] i2c_readback;
-    wire i2c_ready;
-
-    //shared GPIO core signals
-    wire [31:0] gpio_readback;
-
-    ///////////////////////////////////////////////////////////////////////////
-    // Misc Registers - persistent across resets
-    ///////////////////////////////////////////////////////////////////////////
-    wire [31:0] config_word0;
-    setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0
-     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0));
-
-    wire [31:0] config_word1;
-    setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1
-     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1));
-
-    wire clock_sync_inv, clock_sync_enb;
-    setting_reg #(.my_addr(SR_MISC+2), .width(2)) sr_misc_clock_sync
-     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
-     .out({clock_sync_inv, clock_sync_enb}));
-
-    ///////////////////////////////////////////////////////////////////////////
-    // Settings Bus and Readback
-    ///////////////////////////////////////////////////////////////////////////
-    user_settings #(.BASE(SR_USER_REGS)) user_settings
-     (.clk(clk),.rst(reset),
-      .set_stb(set_stb), .set_addr(set_addr),.set_data(set_data),
-      .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) );
-
-    wire [35:0] ctrl_out_data, ctrl_int_data;
-    wire ctrl_out_src_rdy, ctrl_out_dst_rdy;
-    wire ctrl_int_src_rdy, ctrl_int_dst_rdy;
-
-    fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo
-     (.clk(clk), .reset(reset), .clear(1'b0),
-      .datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(),
-      .dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied());
-
-    wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS;
-
-    wire [31:0] sfc_debug;
-    settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc
-    (
-        .clock(clk), .reset(reset), .clear(1'b0),
-        .vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready),
-        .in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy),
-        .out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy),
-        .strobe(set_stb), .addr(set_addr), .data(set_data),
-        .word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback),
-        .word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff),
-        .word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]),
-        .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff),
-        .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
-        .debug(sfc_debug)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-    // Time Core
-    ///////////////////////////////////////////////////////////////////////////
-    time_64bit #(.BASE(SR_TIME64)) time_64bit
-     (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps),
-      .exp_time_in(0));
-
-    assign clock_sync = (clock_sync_enb)? (pps_in ^ clock_sync_inv) : 1'b0;
-
-    ///////////////////////////////////////////////////////////////////////////
-    // SPI Core
-    ///////////////////////////////////////////////////////////////////////////
-    simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff))
-    simple_spi_core (.clock(clk), .reset(reset),
-        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-        .readback(spi_readback), .ready(spi_ready),
-        .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso));
-
-    ///////////////////////////////////////////////////////////////////////////
-    // I2C Core
-    ///////////////////////////////////////////////////////////////////////////
-    wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
-    simple_i2c_core #(.BASE(SR_I2C)) i2c_core
-     (.clock(clk),.reset(reset),
-      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .readback(i2c_readback), .ready(i2c_ready),
-      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
-      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
-
-    // I2C -- Don't use external transistors for open drain, the FPGA implements this
-    IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
-    IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
-
-    ///////////////////////////////////////////////////////////////////////////
-    // GPIO Core
-    ///////////////////////////////////////////////////////////////////////////
-    gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
-    gpio_atr(.clk(clk),.reset(reset),
-        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-        .rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX ADC Frontend, does IQ Balance, DC Offset, muxing
-
-   wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
-
-   rx_frontend #(.BASE(SR_RX_FE)) rx_frontend
-     (.clk(clk),.rst(reset),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_a({rx_i,4'b00}),.adc_ovf_a(0),
-      .adc_b({rx_q,4'b00}),.adc_ovf_b(0),
-      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx), .debug());
-
-   // /////////////////////////////////////////////////////////////////////////
-   // DSP RX *
-
-    wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0];
-    wire rx_int2_src_rdy [NUM_RX_DSPS-1:0];
-    wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0];
-
-    genvar dspno;
-    generate
-    for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps
-
-        wire [31:0] sample_rx;
-        wire strobe_rx, clear_rx;
-        wire [35:0] vita_rx_data;
-        wire vita_rx_src_rdy, vita_rx_dst_rdy;
-        wire [35:0] int_rx_data;
-        wire int_rx_src_rdy, int_rx_dst_rdy;
-
-       ddc_chain #(.BASE(SR_RX_DSP0+dspno*32), .DSPNO(dspno)) ddc_chain
-         (.clk(clk), .rst(reset), .clr(clear_rx),
-          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-          .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx),
-          .debug() );
-
-        vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain
-         (.clk(clk),.reset(reset),
-          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-          .vita_time(vita_time), .overrun(),
-          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx),
-          .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy),
-          .debug() );
-
-        fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo
-         (.clk(clk), .reset(reset), .clear(1'b0),
-          .datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(),
-          .dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied());
-
-        if (dspno == 0) begin
-            assign rx_int2_data[dspno] = int_rx_data;
-            assign rx_int2_src_rdy[dspno] = int_rx_src_rdy;
-            assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno];
-        end
-        else begin
-            fifo36_mux #(.prio(0)) // No priority, fair sharing
-            combine_rx_dsps (
-                .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
-                .data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]),
-                .data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy),
-                .data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno])
-            );
-        end
-
-    end
-    endgenerate
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX Stream muxing
-
-    wire [35:0] rx_int3_data;
-    wire rx_int3_src_rdy, rx_int3_dst_rdy;
-
-    fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined
-         (.clk(clk), .reset(reset), .clear(1'b0),
-          .datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(),
-          .dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied());
-
-    generate
-    if (USE_PACKET_PADDER) begin
-    packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36(
-        .clk(clk), .reset(reset),
-        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-        .data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
-        .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy),
-        .always_flush(~dsp_rx_run));
-    end
-    else begin
-        assign rx_data = rx_int3_data;
-        assign rx_src_rdy = rx_int3_src_rdy;
-        assign rx_int3_dst_rdy = rx_dst_rdy;
-    end
-    endgenerate
-
-    ///////////////////////////////////////////////////////////////////////////
-    // MUX for TX async and resp data
-    ///////////////////////////////////////////////////////////////////////////
-    wire [35:0] tx_err_data, resp_data_int;
-    wire tx_err_src_rdy, resp_src_rdy_int;
-    wire tx_err_dst_rdy, resp_dst_rdy_int;
-
-    fifo36_mux #(.prio(0)) // No priority, fair sharing
-    combine_async_and_resp (
-        .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
-        .data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy),
-        .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
-        .data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int)
-    );
-
-    fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo
-     (.clk(clk), .reset(reset), .clear(1'b0),
-      .datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(),
-      .dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied());
-
-   // ///////////////////////////////////////////////////////////////////////////////////
-   // DSP TX
-
-   wire [23:0] 	 tx_fe_i, tx_fe_q;
-   wire [31:0]   sample_tx;
-   wire strobe_tx, clear_tx;
-
-`ifdef DISABLE_TX_DSP
-    assign tx_dst_rdy = 1; //null sink
-    assign run_tx = 0;
-    assign tx_i = 0;
-    assign tx_q = 0;
-`else
-   vita_tx_chain #(.BASE(SR_TX_CTRL),
-		   .FIFOSIZE(DSP_TX_FIFOSIZE),
-		   .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE),
-		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
-		   .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
-		   .DSP_NUMBER(0))
-   vita_tx_chain
-     (.clk(clk), .reset(reset),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time),
-      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
-      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(), .run(run_tx), .clear_o(clear_tx),
-      .debug());
-
-   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(clk), .rst(reset), .clr(clear_tx),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
-      .debug() );
-
-   tx_frontend #(.BASE(SR_TX_FE), .WIDTH_OUT(14)) tx_frontend
-     (.clk(clk), .rst(reset),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
-      .dac_a(tx_i), .dac_b(tx_q));
-`endif
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Debug circuitry
-
-   assign debug_clk = 2'b11;
-   assign debug = 32'hffffffff;
-
-endmodule // u1plus_core