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authorJosh Blum <josh@joshknows.com>2013-03-25 16:08:03 -0700
committerJosh Blum <josh@joshknows.com>2013-03-25 16:08:03 -0700
commit8488eb09d7db13f67f38dc986b191fd6f3eeea2d (patch)
tree5d5026f8fb62b09332e49d72d2bbbe7a97881b94 /fpga/usrp2/top/B100
parent55d450ba11d8ae46734e291d2876a4a2c9eaaba3 (diff)
parent404a84fcef665d262eee09ba10c841acdd7cbdf2 (diff)
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Merge branch 'maint'
Diffstat (limited to 'fpga/usrp2/top/B100')
-rw-r--r--fpga/usrp2/top/B100/timing.ucf7
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
2 files changed, 7 insertions, 2 deletions
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
index c4404e1d0..7b212a9a6 100644
--- a/fpga/usrp2/top/B100/timing.ucf
+++ b/fpga/usrp2/top/B100/timing.ucf
@@ -15,5 +15,10 @@ INST "GPIF_SLOE" TNM = gpif_net_out;
INST "GPIF_SLRD" TNM = gpif_net_out;
INST "GPIF_PKTEND" TNM = gpif_net_out;
-TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING;
+TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING;
TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;
+
+TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
+
+NET PPS_IN TIG;
+NET debug_led* TIG;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 423282153..302565101 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -71,7 +71,7 @@ module u1plus_core
localparam SR_GPIO = 224; // 5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd11, 16'd1}; //major, minor
+ localparam compat_num = {16'd11, 16'd2}; //major, minor
//assign run signals used for ATR logic
wire [NUM_RX_DSPS-1:0] run_rx_n;