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| author | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
| commit | 3ddbcb6078593c39cb0e4bc8f9769f818a61466f (patch) | |
| tree | 408e3f6a64e31b7d830b9f884ecebdaf100a5d2d /fpga/usrp2/top/B100/timing.ucf | |
| parent | 1fab7e9d477aa98e489400c25a08358952c69c90 (diff) | |
| parent | ace4489066d1621a09e70650a00d736f0b03ed8c (diff) | |
| download | uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.gz uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.bz2 uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.zip | |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/B100/timing.ucf')
| -rw-r--r-- | fpga/usrp2/top/B100/timing.ucf | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf index b2a455f6d..96c47cf2c 100644 --- a/fpga/usrp2/top/B100/timing.ucf +++ b/fpga/usrp2/top/B100/timing.ucf @@ -3,3 +3,12 @@ TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; NET "IFCLK" TNM_NET = "IFCLK"; TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; + +#constrain FX2 IO +NET "GPIF_D<*>" MAXDELAY = 5.5 ns; +NET "GPIF_CTL<*>" MAXDELAY = 5.5 ns; +NET "GPIF_ADR<*>" MAXDELAY = 5.5ns; +NET "GPIF_SLWR" MAXDELAY = 5.5 ns; +NET "GPIF_SLRD" MAXDELAY = 5.5 ns; +NET "GPIF_SLOE" MAXDELAY = 5.5 ns; +NET "GPIF_PKTEND" MAXDELAY = 5.5 ns; |