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| author | Josh Blum <josh@joshknows.com> | 2012-02-17 16:55:59 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-17 16:55:59 -0800 |
| commit | ace4489066d1621a09e70650a00d736f0b03ed8c (patch) | |
| tree | f02b34b70da9e9beb0f34dc5e64d48daa5aa4bf6 /fpga/usrp2/top/B100/Makefile.B100 | |
| parent | 8f8ac3397aaa85b64aaa8722efdc1c0c40e93052 (diff) | |
| parent | 2e37dd87234e5beddd6f76fcda714916f761f812 (diff) | |
| download | uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.tar.gz uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.tar.bz2 uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/B100/Makefile.B100')
| -rw-r--r-- | fpga/usrp2/top/B100/Makefile.B100 | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100 index 90dd25942..3cdbb62c0 100644 --- a/fpga/usrp2/top/B100/Makefile.B100 +++ b/fpga/usrp2/top/B100/Makefile.B100 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -7,7 +7,14 @@ ################################################## TOP_MODULE := B100 BUILD_DIR := build-B100/ -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## include ../Makefile.common include ../../fifo/Makefile.srcs @@ -50,7 +57,7 @@ SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ $(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ -$(GPIF_SRCS) +$(GPIF_SRCS) $(CUSTOM_SRCS) ################################################## # Process Properties @@ -63,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_MOD_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |