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| author | Josh Blum <josh@joshknows.com> | 2012-03-11 14:06:48 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-11 14:06:48 -0700 |
| commit | 38b138b3f31dfaaa4203d82e73be352a03f59280 (patch) | |
| tree | 338a44199de06d7d94a18ca203338b8e418a00fb /fpga/usrp2/top/B100/Makefile.B100 | |
| parent | b61f4ad603b43e8c257bf4bcca924368d5573c92 (diff) | |
| parent | b4173387dd0adb27cc267b22dc57258d44fafa84 (diff) | |
| download | uhd-38b138b3f31dfaaa4203d82e73be352a03f59280.tar.gz uhd-38b138b3f31dfaaa4203d82e73be352a03f59280.tar.bz2 uhd-38b138b3f31dfaaa4203d82e73be352a03f59280.zip | |
Merge branch 'fpga_master'
Diffstat (limited to 'fpga/usrp2/top/B100/Makefile.B100')
| -rw-r--r-- | fpga/usrp2/top/B100/Makefile.B100 | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100 index 3cdbb62c0..48dc7dfd3 100644 --- a/fpga/usrp2/top/B100/Makefile.B100 +++ b/fpga/usrp2/top/B100/Makefile.B100 @@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_MOD_DEFS)" +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |