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authorMatt Ettus <matt@ettus.com>2011-07-28 12:08:23 -0700
committerMatt Ettus <matt@ettus.com>2011-07-28 12:08:23 -0700
commit16f33c73b3a3303d183ebaabcb5fe968bb31c4e8 (patch)
tree4510a63d506a338344c67c792fd7cee4e7883f22 /fpga/usrp2/timing
parent003664fe4e74d6c80cea1c6b06cbd1d1233377f6 (diff)
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vrt: delay the late signal to help with timing
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