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| author | Josh Blum <josh@joshknows.com> | 2012-03-15 17:57:18 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-16 11:29:18 -0700 |
| commit | 6d70e5b3ad4c973a798dd00335fb8785b8c84ff3 (patch) | |
| tree | 3874fc406285c9c28448fb69cfadfb5fa0f02517 /fpga/usrp2/testbench/cmdfile | |
| parent | 28e0a0e38cecdb3e05c9a15ed43bef1cfce7734b (diff) | |
| download | uhd-6d70e5b3ad4c973a798dd00335fb8785b8c84ff3.tar.gz uhd-6d70e5b3ad4c973a798dd00335fb8785b8c84ff3.tar.bz2 uhd-6d70e5b3ad4c973a798dd00335fb8785b8c84ff3.zip | |
spi core: ready logic low one cycle earlier
FIFO ctrl can poke registers every other cycle,
the extra time to register not ready for spi core was too long.
And it with ~trigger to get the not-ready one cycle earlier,
so FIFO ctrl can block on the 2nd potential spi transaction.
Diffstat (limited to 'fpga/usrp2/testbench/cmdfile')
0 files changed, 0 insertions, 0 deletions