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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
| commit | 05d77f772317de5d925301aa11bb9a880656dd05 (patch) | |
| tree | 0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp2/testbench/cmdfile | |
| parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
| download | uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2 uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip | |
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp2/testbench/cmdfile')
| -rw-r--r-- | fpga/usrp2/testbench/cmdfile | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/fpga/usrp2/testbench/cmdfile b/fpga/usrp2/testbench/cmdfile new file mode 100644 index 000000000..8083eb92a --- /dev/null +++ b/fpga/usrp2/testbench/cmdfile @@ -0,0 +1,27 @@ + +# My stuff +-y . +-y ../top/u2_core +-y ../control_lib +-y ../control_lib/newfifo +-y ../serdes +-y ../sdr_lib +-y ../timing +-y ../coregen +-y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim + +# Models +-y ../models +-y ../models/CY7C1356C + +# Open Cores +-y ../opencores/8b10b +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_pic/rtl + |