Merge branch 'packet_router_2nd_dsp' into next

2 files changed, 50 insertions, 78 deletions

diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
index efcf89276..b783729d5 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -1,7 +1,7 @@
 
 module simple_gemac_wrapper
   #(parameter RXFIFOSIZE=9,
-    parameter TXFIFOSIZE=6)
+    parameter TXFIFOSIZE=9)
    (input clk125, input reset,
     // GMII
     output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
@@ -30,7 +30,9 @@ module simple_gemac_wrapper
    wire 	  pause_req;
    wire 	  pause_request_en, pause_respect_en;
    wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
-   
+
+   wire [31:0] 	  debug_state;
+      
    wire 	  tx_reset, rx_reset;
    reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
    reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
@@ -49,7 +51,8 @@ module simple_gemac_wrapper
       .rx_clk(rx_clk), .rx_data(rx_data),
       .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
       .tx_clk(tx_clk), .tx_data(tx_data), 
-      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .debug(debug_state)
       );
    
    simple_gemac_wb simple_gemac_wb
@@ -65,14 +68,12 @@ module simple_gemac_wrapper
 
    // RX FIFO Chain
    wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire [7:0] 	  rx_ll_data;
    
-   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
-   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-   
-   wire [7:0] 	  rx_ll_data, rx_ll_data2;
-   
-   wire [35:0] 	  rx_f36_data_int1;
-   wire 	  rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+   wire [18:0] 	  rx_f19_data_int1, rx_f19_data_int2;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
+   wire [35:0] 	  rx_f36_data_int;
+   wire 	  rx_f36_src_rdy_int, rx_f36_dst_rdy_int;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -80,86 +81,69 @@ module simple_gemac_wrapper
       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
 
-   ll8_shortfifo rx_sfifo
+   ll8_to_fifo19 ll8_to_fifo19
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
-      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
+      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
 
-   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
-   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
-   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
-   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
-   
-   ll8_to_fifo36 ll8_to_fifo36
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
+      .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
+
+   fifo19_to_fifo36 rx_fifo19_to_fifo36
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
-      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
-      .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+      .f19_datain(rx_f19_data_int2),  .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2),
+      .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) );
 
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
+     (.wclk(rx_clk), .datain(rx_f36_data_int), 
+      .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f36_data), 
       .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
    
    // TX FIFO Chain
    wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
-   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [7:0] 	  tx_ll_data;
    wire [35:0] 	  tx_f36_data_int1;
    wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
    
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
-     (.wclk(sys_clk), .datain(tx_f36_data), 
-      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
-      .rclk(tx_clk), .dataout(tx_f36_data_int1), 
-      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
+     (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
+      .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), 
+      .arst(reset));
    
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
-      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
-      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy));
 
-   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
-   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
-   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
-   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
-   
-   ll8_shortfifo tx_sfifo
-     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
-      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
-      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
-      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
-      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
-   
    ll8_to_txmac ll8_to_txmac
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
       .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
 
+   // Flow Control
    flow_ctrl_rx flow_ctrl_rx
      (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
       .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
       .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
    
    wire [31:0] 	  debug_tx, debug_rx;
-   
+
    assign debug_tx  = { { tx_ll_data },
-			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
-			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 },
 			{ tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
 			{ tx_data} };
    assign debug_rx  = { { rx_ll_data },
-			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
-			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
-			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
+			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]},
 			{ rx_data} };
 
    assign debug  = debug_rx;
    
 endmodule // simple_gemac_wrapper
+
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
index 6cdbd1a59..c155b7d41 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
@@ -68,14 +68,10 @@ module simple_gemac_wrapper19
 
    // RX FIFO Chain
    wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire [7:0] 	  rx_ll_data;
    
-   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
-   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-   
-   wire [7:0] 	  rx_ll_data, rx_ll_data2;
-   
-   wire [18:0] 	  rx_f19_data_int1;
-   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1;
+   wire [18:0] 	  rx_f19_data_int1, rx_f19_data_int2;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -83,28 +79,21 @@ module simple_gemac_wrapper19
       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
 
-   ll8_shortfifo rx_sfifo
-     (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
-      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
-
-   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
-   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
-   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
-   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
-   
    ll8_to_fifo19 ll8_to_fifo19
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
-      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
       .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
 
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
+      .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
+
    //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f19_data_int1), 
-      .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space),
+     (.wclk(rx_clk), .datain(rx_f19_data_int2), 
+      .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f19_data), 
       .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset));
    
@@ -160,8 +149,7 @@ module simple_gemac_wrapper19
 			{ tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
 			{ tx_data} };
    assign debug_rx  = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] },
-			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
-			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
 			{ rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
 			{ rx_data} };