aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp2/simple_gemac/ethrx_realign.v
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2011-03-17 13:53:48 -0700
committerJosh Blum <josh@joshknows.com>2011-03-17 13:53:48 -0700
commitee424d797fc37a8c3c2a82a58218bf1e85456226 (patch)
tree74b179d55122df0a156f82ef25dd42895bb52487 /fpga/usrp2/simple_gemac/ethrx_realign.v
parentb52877b3d9af48ecde6f5378755e8c2337a41921 (diff)
parentbe2c1b95c1d6f4ad2ea663bb926a04463edb9358 (diff)
downloaduhd-ee424d797fc37a8c3c2a82a58218bf1e85456226.tar.gz
uhd-ee424d797fc37a8c3c2a82a58218bf1e85456226.tar.bz2
uhd-ee424d797fc37a8c3c2a82a58218bf1e85456226.zip
Merge branch 'fpga_memory_reorg' into usrp2/new_reg_map
Diffstat (limited to 'fpga/usrp2/simple_gemac/ethrx_realign.v')
-rw-r--r--fpga/usrp2/simple_gemac/ethrx_realign.v72
1 files changed, 72 insertions, 0 deletions
diff --git a/fpga/usrp2/simple_gemac/ethrx_realign.v b/fpga/usrp2/simple_gemac/ethrx_realign.v
new file mode 100644
index 000000000..0a369c914
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/ethrx_realign.v
@@ -0,0 +1,72 @@
+
+// NOTE: Will not work with single-line frames
+
+module ethrx_realign
+ (input clk, input reset, input clear,
+ input [35:0] datain, input src_rdy_i, output dst_rdy_o,
+ output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+ reg [1:0] state;
+ reg [15:0] held;
+ reg [1:0] held_occ;
+
+ wire xfer_in = src_rdy_i & dst_rdy_o;
+ wire xfer_out = src_rdy_o & dst_rdy_i;
+
+ wire sof_in = datain[32];
+ wire eof_in = datain[33];
+ wire [1:0] occ_in = datain[35:34];
+ wire sof_out, eof_out;
+ wire [1:0] occ_out;
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ held <= 0;
+ held_occ <= 0;
+ end
+ else if(xfer_in)
+ begin
+ held <= datain[15:0];
+ held_occ <= datain[35:34];
+ end
+
+ localparam RE_IDLE = 0;
+ localparam RE_HELD = 1;
+ localparam RE_DONE = 2;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= RE_IDLE;
+ else
+ case(state)
+ RE_IDLE :
+ if(src_rdy_i & dst_rdy_i)
+ if(eof_in)
+ state <= RE_DONE;
+ else
+ state <= RE_HELD;
+
+ RE_HELD :
+ if(src_rdy_i & dst_rdy_i & eof_in)
+ if((occ_in==0)|(occ_in==3))
+ state <= RE_DONE;
+ else
+ state <= RE_IDLE;
+
+ RE_DONE :
+ if(dst_rdy_i)
+ state <= RE_IDLE;
+
+ endcase // case (state)
+
+
+ assign sof_out = (state == RE_IDLE);
+ assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2);
+ assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) :
+ (occ_in == 1) ? 3 : 0;
+
+ assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]};
+ assign src_rdy_o = (state == RE_DONE) | src_rdy_i;
+ assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD));
+endmodule // ethrx_realign