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authorWade Fife <wade.fife@ettus.com>2021-03-09 15:38:58 -0600
committerAaron Rossetto <aaron.rossetto@ni.com>2021-06-03 11:26:54 -0500
commitc6035320215f270d7658cfb6195a96a0b84d6aa7 (patch)
treefa0ee70b261291022d723e9e6f85512975bf89cb /fpga/usrp2/serdes
parentc64258e09b221d0bfeb55e01085a20e37c5b62ba (diff)
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fpga: lib: Pipeline ctrlport_timer
This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
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