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author | Wade Fife <wade.fife@ettus.com> | 2021-03-09 15:38:58 -0600 |
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committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
commit | c6035320215f270d7658cfb6195a96a0b84d6aa7 (patch) | |
tree | fa0ee70b261291022d723e9e6f85512975bf89cb /fpga/usrp2/serdes | |
parent | c64258e09b221d0bfeb55e01085a20e37c5b62ba (diff) | |
download | uhd-c6035320215f270d7658cfb6195a96a0b84d6aa7.tar.gz uhd-c6035320215f270d7658cfb6195a96a0b84d6aa7.tar.bz2 uhd-c6035320215f270d7658cfb6195a96a0b84d6aa7.zip |
fpga: lib: Pipeline ctrlport_timer
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Diffstat (limited to 'fpga/usrp2/serdes')
0 files changed, 0 insertions, 0 deletions