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| author | Josh Blum <josh@joshknows.com> | 2011-11-11 17:53:04 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-11-11 17:53:04 -0800 |
| commit | b23126d3a0fca7d56a933e7f2f0011a9d625b006 (patch) | |
| tree | 175055e4af6ec2a950b5e2b331e0e85a9363db4a /fpga/usrp2/sdr_lib | |
| parent | 88e02e0d55f7a80180402c7c86132d22a43ec551 (diff) | |
| parent | 52b552f43bc1925ce27b4f49dff1669cb019ecfc (diff) | |
| download | uhd-b23126d3a0fca7d56a933e7f2f0011a9d625b006.tar.gz uhd-b23126d3a0fca7d56a933e7f2f0011a9d625b006.tar.bz2 uhd-b23126d3a0fca7d56a933e7f2f0011a9d625b006.zip | |
Merge branch 'fpga_cal_work' into calibration
Diffstat (limited to 'fpga/usrp2/sdr_lib')
| -rw-r--r-- | fpga/usrp2/sdr_lib/rx_frontend.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/sdr_lib/tx_frontend.v | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v index 5b64737b2..ebe19240c 100644 --- a/fpga/usrp2/sdr_lib/rx_frontend.v +++ b/fpga/usrp2/sdr_lib/rx_frontend.v @@ -55,12 +55,12 @@ module rx_frontend add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), - .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1), .sum(i_out), .strobe_out()); add2_and_clip_reg #(.WIDTH(24)) add_clip_q (.clk(clk), .rst(rst), - .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1), .sum(q_out), .strobe_out()); end // if (IQCOMP_EN == 1) else diff --git a/fpga/usrp2/sdr_lib/tx_frontend.v b/fpga/usrp2/sdr_lib/tx_frontend.v index 17a6e35e0..dea8e010a 100644 --- a/fpga/usrp2/sdr_lib/tx_frontend.v +++ b/fpga/usrp2/sdr_lib/tx_frontend.v @@ -50,12 +50,12 @@ module tx_frontend add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), - .in1(tx_i), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1), .sum(i_bal), .strobe_out()); add2_and_clip_reg #(.WIDTH(24)) add_clip_q (.clk(clk), .rst(rst), - .in1(tx_q), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1), .sum(q_bal), .strobe_out()); // DC Offset |