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| author | Josh Blum <josh@joshknows.com> | 2013-08-28 17:19:40 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-08-28 17:19:40 -0700 |
| commit | 528f2ec3028ec735fe4be39a1087c77068c61860 (patch) | |
| tree | f4bc94dc9e7bf988882a7286a4cfe9d0a934ebd8 /fpga/usrp2/sdr_lib | |
| parent | 2d4c77489f540a6978497d25dd3e316a2f16e9ad (diff) | |
| parent | 714673c7437fcd863d2bfdb8b20689d6a6d0f577 (diff) | |
| download | uhd-528f2ec3028ec735fe4be39a1087c77068c61860.tar.gz uhd-528f2ec3028ec735fe4be39a1087c77068c61860.tar.bz2 uhd-528f2ec3028ec735fe4be39a1087c77068c61860.zip | |
Merge branch 'fpga_master' into master_converter_work
Diffstat (limited to 'fpga/usrp2/sdr_lib')
| -rw-r--r-- | fpga/usrp2/sdr_lib/dspengine_16to8.v | 6 | ||||
| -rw-r--r-- | fpga/usrp2/sdr_lib/dspengine_8to16.v | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/fpga/usrp2/sdr_lib/dspengine_16to8.v b/fpga/usrp2/sdr_lib/dspengine_16to8.v index 448c57d35..1d6746dd1 100644 --- a/fpga/usrp2/sdr_lib/dspengine_16to8.v +++ b/fpga/usrp2/sdr_lib/dspengine_16to8.v @@ -1,5 +1,5 @@ -// Copyright 2011-2012 Ettus Research LLC +// Copyright 2011-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -181,8 +181,8 @@ module dspengine_16to8 assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } : (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } : - (last_o&~even_o) ? {4'h0, 16'd0, i8, q8 } : - {4'h0, i8, q8, i8_reg, q8_reg }; + (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } : + {4'h0, i8_reg, q8_reg, i8, q8 }; assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr; diff --git a/fpga/usrp2/sdr_lib/dspengine_8to16.v b/fpga/usrp2/sdr_lib/dspengine_8to16.v index 85187d78d..64246ac13 100644 --- a/fpga/usrp2/sdr_lib/dspengine_8to16.v +++ b/fpga/usrp2/sdr_lib/dspengine_8to16.v @@ -1,5 +1,5 @@ -// Copyright 2012 Ettus Research LLC +// Copyright 2012-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -75,13 +75,13 @@ module dspengine_8to16 wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd; reg [7:0] i8_0, q8_0; - wire [7:0] i8_1 = access_dat_i[31:24]; - wire [7:0] q8_1 = access_dat_i[23:16]; + wire [7:0] i8_1 = access_dat_i[15:8]; + wire [7:0] q8_1 = access_dat_i[7:0]; reg skip; always @(posedge clk) - { i8_0, q8_0 } <= access_dat_i[15:0]; + { i8_0, q8_0 } <= access_dat_i[31:16]; always @(posedge clk) if(reset | clear) |