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| author | Josh Blum <josh@joshknows.com> | 2010-08-10 23:29:22 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-08-10 23:29:22 -0700 |
| commit | 293ccdccd1e111942e9cc48ab87690da5202e406 (patch) | |
| tree | 4e861ca41fabc1e2664b7d0807242ab9c61544fd /fpga/usrp2/sdr_lib | |
| parent | 1301d665d621358ec6eccb41a020a4689cb0b566 (diff) | |
| parent | 9e419c7b7f35062ceb2ed4e508cadb163067593f (diff) | |
| download | uhd-293ccdccd1e111942e9cc48ab87690da5202e406.tar.gz uhd-293ccdccd1e111942e9cc48ab87690da5202e406.tar.bz2 uhd-293ccdccd1e111942e9cc48ab87690da5202e406.zip | |
usrp-e: merged master, does not build
Diffstat (limited to 'fpga/usrp2/sdr_lib')
| -rw-r--r-- | fpga/usrp2/sdr_lib/dsp_core_tx.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v index 22d3d44a3..79d92c9b3 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_tx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v @@ -29,11 +29,11 @@ module dsp_core_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); - setting_reg #(.my_addr(BASE+2)) sr_2 + setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); - setting_reg #(.my_addr(BASE+4)) sr_4 + setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); |