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author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:17:54 -0700 |
commit | 17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9 (patch) | |
tree | e2d0d39d6b44b72c759b8be1380b2024de50bdf6 /fpga/usrp2/sdr_lib/round.v | |
parent | 60933a242cce0b1ec45e9f948e3da9ab72b2fd90 (diff) | |
parent | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (diff) | |
download | uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.gz uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.tar.bz2 uhd-17fabccfe4be79f3a5a0a3d7ab14ea72a791ecd9.zip |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/sdr_lib/round.v')
-rw-r--r-- | fpga/usrp2/sdr_lib/round.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga/usrp2/sdr_lib/round.v b/fpga/usrp2/sdr_lib/round.v index c4f9ec9cd..7a137d702 100644 --- a/fpga/usrp2/sdr_lib/round.v +++ b/fpga/usrp2/sdr_lib/round.v @@ -26,8 +26,10 @@ module round #(parameter bits_in=0, parameter bits_out=0) (input [bits_in-1:0] in, - output [bits_out-1:0] out); + output [bits_out-1:0] out, + output [bits_in-bits_out:0] err); assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + assign err = in - {out,{(bits_in-bits_out){1'b0}}}; endmodule // round |