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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/sdr_lib/integrate.v
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
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Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/sdr_lib/integrate.v')
-rw-r--r--fpga/usrp2/sdr_lib/integrate.v55
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diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v
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-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-
-module integrate
- #(parameter INPUTW = 16,
- parameter ACCUMW = 32,
- parameter OUTPUTW = 16)
-
- (input clk_i,
- input rst_i,
- input ena_i,
-
- input dump_i,
- input [INPUTW-1:0] data_i,
-
- output reg stb_o,
- output reg [OUTPUTW-1:0] integ_o
- );
-
- wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
- reg [ACCUMW-1:0] accum;
-
- always @(posedge clk_i)
- if (rst_i | ~ena_i)
- begin
- accum <= 0;
- integ_o <= 0;
- end
- else
- if (dump_i)
- begin
- integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
- accum <= data_ext;
- end
- else
- accum <= accum + data_ext;
-
- always @(posedge clk_i)
- stb_o <= dump_i;
-
-endmodule // integrate