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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/sdr_lib/hb/mult.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp2/sdr_lib/hb/mult.v')
-rw-r--r--fpga/usrp2/sdr_lib/hb/mult.v16
1 files changed, 16 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/hb/mult.v b/fpga/usrp2/sdr_lib/hb/mult.v
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+
+
+module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
+ input enable_in, output reg enable_out );
+
+ always @(posedge clock)
+ if(enable_in)
+ product <= #1 x*y;
+ else
+ product <= #1 31'd0;
+
+ always @(posedge clock)
+ enable_out <= #1 enable_in;
+
+endmodule // mult
+