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author | Josh Blum <josh@joshknows.com> | 2011-11-07 17:09:07 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2011-11-07 17:09:07 -0800 |
commit | 11f1390bbde65c60f45962acb128cac1ce21e474 (patch) | |
tree | 372f2e426781de9885889bec6aa98697006268ec /fpga/usrp2/sdr_lib/clip_reg.v | |
parent | 902818f50bbd486138a7d4cd2ce9ba3661f4a732 (diff) | |
parent | bcb80c5cf9a2117f9d6d22b8e793ea2ecb68ed1f (diff) | |
download | uhd-11f1390bbde65c60f45962acb128cac1ce21e474.tar.gz uhd-11f1390bbde65c60f45962acb128cac1ce21e474.tar.bz2 uhd-11f1390bbde65c60f45962acb128cac1ce21e474.zip |
Merge branch 'fpga_master' into uhd_next
Diffstat (limited to 'fpga/usrp2/sdr_lib/clip_reg.v')
-rw-r--r-- | fpga/usrp2/sdr_lib/clip_reg.v | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/fpga/usrp2/sdr_lib/clip_reg.v b/fpga/usrp2/sdr_lib/clip_reg.v index d5e98d982..9098fd5b8 100644 --- a/fpga/usrp2/sdr_lib/clip_reg.v +++ b/fpga/usrp2/sdr_lib/clip_reg.v @@ -23,16 +23,24 @@ module clip_reg #(parameter bits_in=0, - parameter bits_out=0) + parameter bits_out=0, + parameter STROBED=1'b0) (input clk, input [bits_in-1:0] in, - output reg [bits_out-1:0] out); + output reg [bits_out-1:0] out, + input strobe_in, + output reg strobe_out); wire [bits_out-1:0] temp; clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp)); + + always @(posedge clk) + strobe_out <= strobe_in; + always @(posedge clk) - out <= temp; + if(strobe_in | ~STROBED) + out <= temp; endmodule // clip_reg |