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authorJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
committerJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
commitedcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch)
tree1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/sdr_lib/Makefile.srcs
parenta89d684ba2b81c6e18d348965dffb919edb56fea (diff)
parent9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts: fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/sdr_lib/Makefile.srcs')
-rw-r--r--fpga/usrp2/sdr_lib/Makefile.srcs37
1 files changed, 37 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/Makefile.srcs b/fpga/usrp2/sdr_lib/Makefile.srcs
new file mode 100644
index 000000000..90eede20f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/Makefile.srcs
@@ -0,0 +1,37 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \
+acc.v \
+add2.v \
+add2_and_round.v \
+add2_and_round_reg.v \
+add2_reg.v \
+cic_dec_shifter.v \
+cic_decim.v \
+cic_int_shifter.v \
+cic_interp.v \
+cic_strober.v \
+clip.v \
+clip_reg.v \
+cordic.v \
+cordic_z24.v \
+cordic_stage.v \
+dsp_core_rx.v \
+dsp_core_rx_old.v \
+dsp_core_tx.v \
+hb_dec.v \
+hb_interp.v \
+round.v \
+round_reg.v \
+rx_control.v \
+rx_dcoffset.v \
+sign_extend.v \
+small_hb_dec.v \
+small_hb_int.v \
+tx_control.v \
+))