aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp2/models/miim_model.v
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
commit05d77f772317de5d925301aa11bb9a880656dd05 (patch)
tree0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp2/models/miim_model.v
parent16818dc98e97b69a028c47e66ebfb16e32565533 (diff)
downloaduhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz
uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2
uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp2/models/miim_model.v')
-rw-r--r--fpga/usrp2/models/miim_model.v14
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga/usrp2/models/miim_model.v b/fpga/usrp2/models/miim_model.v
new file mode 100644
index 000000000..936d99a80
--- /dev/null
+++ b/fpga/usrp2/models/miim_model.v
@@ -0,0 +1,14 @@
+
+// Skeleton PHY interface simulator
+
+module miim_model(input mdc_i,
+ inout mdio,
+ input phy_resetn_i,
+ input phy_clk_i,
+ output phy_intn_o,
+ output [2:0] speed_o);
+
+ assign phy_intn_o = 1; // No interrupts
+ assign speed_o = 3'b100; // 1G mode
+
+endmodule // miim_model