Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 172 insertions, 0 deletions

diff --git a/fpga/usrp2/models/IDDR2.v b/fpga/usrp2/models/IDDR2.v
new file mode 100644
index 000000000..727f1c568
--- /dev/null
+++ b/fpga/usrp2/models/IDDR2.v
@@ -0,0 +1,172 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/IDDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Dual Data Rate Input D Flip-Flop
+// /___/   /\     Filename : IDDR2.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:43:51 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+
+`timescale  1 ps / 1 ps
+
+module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
+    
+    output Q0;
+    output Q1;
+    
+    input C0;
+    input C1;
+    input CE;
+    input D;
+    tri0 GSR = glbl.GSR;
+    input R;
+    input S;
+
+    parameter DDR_ALIGNMENT = "NONE";
+    parameter INIT_Q0 = 1'b0;
+    parameter INIT_Q1 = 1'b0;
+    parameter SRTYPE = "SYNC";
+
+    reg q0_out, q1_out;
+    reg q0_out_int, q1_out_int;
+    reg q0_c1_out_int, q1_c0_out_int;
+    
+    buf buf_q0 (Q0, q0_out);
+    buf buf_q1 (Q1, q1_out);
+
+    
+    initial begin
+
+	if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
+	    $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q0);
+	    $finish;
+	end
+	
+    	if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
+	    $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q1);
+	    $finish;
+	end
+
+    	if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
+	    $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s.  Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
+	    $finish;
+	end
+	
+	if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
+	    $display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
+	    $finish;
+	end
+
+    end // initial begin
+
+
+    always @(GSR or R or S) begin
+
+	if (GSR == 1) begin
+
+	    assign q0_out_int = INIT_Q0;
+	    assign q1_out_int = INIT_Q1;
+	    assign q0_c1_out_int = INIT_Q0;
+	    assign q1_c0_out_int = INIT_Q1;
+
+	end
+	else begin
+	    
+	    deassign q0_out_int;
+	    deassign q1_out_int;
+	    deassign q0_c1_out_int;
+	    deassign q1_c0_out_int;
+	    
+	    if (SRTYPE == "ASYNC") begin
+		if (R == 1) begin
+		    assign q0_out_int = 0;
+		    assign q1_out_int = 0;
+		    assign q0_c1_out_int = 0;
+		    assign q1_c0_out_int = 0;
+		end
+		else if (R == 0 && S == 1) begin
+		    assign q0_out_int = 1;
+		    assign q1_out_int = 1;
+		    assign q0_c1_out_int = 1;
+		    assign q1_c0_out_int = 1;
+		end
+	    end // if (SRTYPE == "ASYNC")
+	    
+	end // if (GSR == 1'b0)
+	
+    end // always @ (GSR or R or S)
+
+	    
+    always @(posedge C0) begin
+ 	if (R == 1 && SRTYPE == "SYNC") begin
+	    q0_out_int <= 0;
+	    q1_c0_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q0_out_int <= 1;
+	    q1_c0_out_int <= 1;
+	end
+	else if (CE == 1 && R == 0 && S == 0) begin
+            q0_out_int <= D;
+	    q1_c0_out_int <= q1_out_int;
+	end
+    end // always @ (posedge C0)
+
+    
+    always @(posedge C1) begin
+ 	if (R == 1 && SRTYPE == "SYNC") begin
+	    q1_out_int <= 0;
+	    q0_c1_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q1_out_int <= 1;
+	    q0_c1_out_int <= 1;
+	end
+	else if (CE == 1 && R == 0 && S == 0) begin
+            q1_out_int <= D;
+	    q0_c1_out_int <= q0_out_int;
+	end
+    end // always @ (posedge C1)
+    
+    
+    always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int) begin
+
+	case (DDR_ALIGNMENT)
+	    "NONE" : begin
+		       q0_out <= q0_out_int;
+		       q1_out <= q1_out_int;
+	             end
+	    "C0" : begin
+	               q0_out <= q0_out_int;
+	               q1_out <= q1_c0_out_int;
+	           end
+	    "C1" : begin
+		       q0_out <= q0_c1_out_int;
+                       q1_out <= q1_out_int;
+	           end
+	endcase // case(DDR_ALIGNMENT)
+
+    end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int)
+    
+
+    specify
+
+	if (C0) (C0 => Q0) = (100, 100);
+	if (C0) (C0 => Q1) = (100, 100);
+	if (C1) (C1 => Q1) = (100, 100);
+	if (C1) (C1 => Q0) = (100, 100);
+	specparam PATHPULSE$ = 0;
+
+    endspecify
+
+endmodule // IDDR2
+