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author | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
commit | 45c1af8152d02cd7d4e5d5d603e1cca65f6dd539 (patch) | |
tree | 2a48c592cef637476c2566fc64675dcdac8a7b05 /fpga/usrp2/models/IBUFGDS.v | |
parent | 7a1824e8fddadd915e2d7490a8b57764b815b09f (diff) | |
parent | 295c7e7b98df98989f3fb4505e44f0be52813d81 (diff) | |
download | uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.gz uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.bz2 uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.zip |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/models/IBUFGDS.v')
-rw-r--r-- | fpga/usrp2/models/IBUFGDS.v | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/fpga/usrp2/models/IBUFGDS.v b/fpga/usrp2/models/IBUFGDS.v new file mode 100644 index 000000000..01c108c8d --- /dev/null +++ b/fpga/usrp2/models/IBUFGDS.v @@ -0,0 +1,87 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.8 2007/07/26 23:22:55 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer +// /___/ /\ Filename : IBUFGDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/26/07 - Add else to handle x case for o_out (CR 424214). +// End Revision + + +`timescale 1 ps / 1 ps + + +module IBUFGDS (O, I, IB); + + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + end + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx && IB == 1'bx) + o_out <= 1'bx; + end + +endmodule + + |