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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
| commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
| tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/models/CY7C1356C/readme.txt | |
| parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
| parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
| download | uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.gz uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.bz2 uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.zip | |
Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/models/CY7C1356C/readme.txt')
| -rw-r--r-- | fpga/usrp2/models/CY7C1356C/readme.txt | 33 |
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diff --git a/fpga/usrp2/models/CY7C1356C/readme.txt b/fpga/usrp2/models/CY7C1356C/readme.txt new file mode 100644 index 000000000..3578c80dc --- /dev/null +++ b/fpga/usrp2/models/CY7C1356C/readme.txt @@ -0,0 +1,33 @@ +***************************
+Cypress Semiconductor
+MPD Applications
+Verilog model for NoBL SRAM CY7C1356
+Created: August 04, 2004
+Rev: 1.0
+***************************
+
+This is the verilog model for the CY7C1356 along with the testbench and test vectors.
+
+Contact support@cypress.com if you have any questions.
+
+This directory has 4 files. including this readme.
+
+1)cy7c1356c.v -> Verilog model for CY7C1356c
+
+2)cy1356.inp -> Test Vector File used for testing the verilog model
+
+3)testbench.v -> Test bench used for testing the verilog model
+
+
+COMPILING METHOD :
+------------------
+
+ verilog +define+<speed_bin> <Main File> <Test bench File>
+
+ Ex:
+ verilog +define+sb133 CY7C1356c.v testbench.v
+
+VERIFIED WITH:
+--------------
+
+VERILOG-XL 2.2
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