Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e

Conflicts:
	.gitignore

1 files changed, 33 insertions, 0 deletions

diff --git a/fpga/usrp2/models/BUFG.v b/fpga/usrp2/models/BUFG.v
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+++ b/fpga/usrp2/models/BUFG.v
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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Global Clock Buffer
+// /___/   /\     Filename : BUFG.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:14 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`timescale  100 ps / 10 ps
+
+
+module BUFG (O, I);
+
+    output O;
+
+    input  I;
+
+	buf B1 (O, I);
+
+
+endmodule
+