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authorJosh Blum <josh@joshknows.com>2013-05-09 17:40:52 -0700
committerJosh Blum <josh@joshknows.com>2013-05-09 17:40:52 -0700
commit845dd30d8ba2113f86ff762e0c848fac9b171655 (patch)
tree8b94ce0d2a7853fe8cdd9449279c0b0830832560 /fpga/usrp2/gpmc
parentb0a4e2ad081cc55ad309d44b59583f0140f87608 (diff)
parent286f0d8d3830417cbf26ac494bb960b4ba735944 (diff)
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Merge branch 'fpga_master' into maint
Diffstat (limited to 'fpga/usrp2/gpmc')
-rw-r--r--fpga/usrp2/gpmc/fifo_to_gpmc.v10
1 files changed, 7 insertions, 3 deletions
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v
index 93341975d..26443a702 100644
--- a/fpga/usrp2/gpmc/fifo_to_gpmc.v
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v
@@ -46,6 +46,7 @@ module fifo_to_gpmc
output reg data_available);
//states for the GPMC side of things
+ wire [17:0] data_o;
reg gpmc_state;
reg [ADDR_WIDTH:1] addr;
reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
@@ -146,11 +147,14 @@ module fifo_to_gpmc
assign dst_rdy_o = fifo_state == FIFO_STATE_FILL;
+ //assign data from bram output
+ assign EM_D = data_o[15:0];
+
//instantiate dual ported bram for async read + write
- ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
+ ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
(.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o),
- .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i[15:0]),.doa(),
+ .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i),.doa(),
.clkb(EM_CLK),.enb(1'b1),.web(1'b0),
- .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(EM_D));
+ .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(data_o));
endmodule // fifo_to_gpmc