Merge branch 'fpga_master' into next

1 files changed, 18 insertions, 13 deletions

diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v
index 645201ef7..4d368ca94 100644
--- a/fpga/usrp2/gpmc/gpmc_wb.v
+++ b/fpga/usrp2/gpmc/gpmc_wb.v
@@ -19,7 +19,7 @@
 
 module gpmc_wb
   (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE,
-   input EM_NCS, input EM_NWE, input EM_NOE,
+   input EM_WE, input EM_OE,
 
    input wb_clk, input wb_rst,
    output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
@@ -27,25 +27,31 @@ module gpmc_wb
    
    // ////////////////////////////////////////////
    // Control Path, Wishbone bus bridge (wb master)
-   reg [1:0] 	cs_del, we_del, oe_del;
+   reg [1:0] we_del, oe_del;
 
    // Synchronize the async control signals
    always @(posedge wb_clk)
-     begin
-	cs_del <= { cs_del[0], EM_NCS };
-	we_del <= { we_del[0], EM_NWE };
-	oe_del <= { oe_del[0], EM_NOE };
+     if (wb_rst) begin
+        we_del <= 2'b0;
+        oe_del <= 2'b0;
      end
+     else begin
+        we_del <= { we_del[0], EM_WE };
+        oe_del <= { oe_del[0], EM_OE };
+     end
+
+    wire writing = we_del == 2'b01;
+    wire reading = oe_del == 2'b01;
 
    always @(posedge wb_clk)
-     if(cs_del == 2'b10)  // Falling Edge
+     if(writing || reading)
        wb_adr_o <= { EM_A, 1'b0 };
 
    always @(posedge wb_clk)
-     if(we_del == 2'b10)  // Falling Edge
+     if(writing)
        begin
-	  wb_dat_mosi <= EM_D_in;
-	  wb_sel_o <= ~EM_NBE;
+          wb_dat_mosi <= EM_D_in;
+          wb_sel_o <= ~EM_NBE;
        end
 
    reg [15:0] EM_D_hold;
@@ -59,14 +65,13 @@ module gpmc_wb
    assign wb_cyc_o = wb_stb_o;
 
    always @(posedge wb_clk)
-     if(~cs_del[0] & (we_del == 2'b10) )
+     if(writing)
        wb_we_o <= 1;
      else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
        wb_we_o <= 0;
 
-   // FIXME should this look at cs_del[1]?
    always @(posedge wb_clk)
-     if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+     if(writing || reading)
        wb_stb_o <= 1;
      else if(wb_ack_i)
        wb_stb_o <= 0;