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authorJosh Blum <josh@joshknows.com>2012-08-31 11:20:17 -0700
committerJosh Blum <josh@joshknows.com>2012-08-31 11:20:17 -0700
commit667dcf0b98bb5a99654cf883fb97d2a549582cff (patch)
tree7c845d7ac3f506c000ab495b1d62d976b816b5cd /fpga/usrp2/gpmc/cross_clock_reader.v
parent05a06254a7f0149425bdda0e5544507bd35a671b (diff)
parent36a7def9aa6cecaa6f3cbf9979544d6fd5848a08 (diff)
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Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/gpmc/cross_clock_reader.v')
-rw-r--r--fpga/usrp2/gpmc/cross_clock_reader.v8
1 files changed, 5 insertions, 3 deletions
diff --git a/fpga/usrp2/gpmc/cross_clock_reader.v b/fpga/usrp2/gpmc/cross_clock_reader.v
index a8366badc..b4cdb79c5 100644
--- a/fpga/usrp2/gpmc/cross_clock_reader.v
+++ b/fpga/usrp2/gpmc/cross_clock_reader.v
@@ -27,18 +27,20 @@ module cross_clock_reader
);
reg [WIDTH-1:0] shadow0, shadow1;
+ reg [2:0] count;
always @(posedge clk) begin
if (rst) begin
out <= DEFAULT;
shadow0 <= DEFAULT;
shadow1 <= DEFAULT;
+ count <= 0;
end
- else if (shadow0 == shadow1) begin
- out <= shadow1;
- end
+ else if (shadow0 == shadow1) count <= count + 1;
+ else count <= 0;
shadow0 <= in;
shadow1 <= shadow0;
+ if (count == 3'b111) out <= shadow1;
end
endmodule //cross_clock_reader