Merge branch 'fpga_next' into next

1 files changed, 13 insertions, 21 deletions

diff --git a/fpga/usrp2/gpif/packet_reframer.v b/fpga/usrp2/gpif/packet_reframer.v
index 923d499ae..8bb8a3678 100644
--- a/fpga/usrp2/gpif/packet_reframer.v
+++ b/fpga/usrp2/gpif/packet_reframer.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -16,7 +16,7 @@
 //
 
 
-// Join vita packets longer than one GPIF frame, drop padding on short frames
+// Join vita packets longer than one GPIF frame
 
 module packet_reframer
   (input clk, input reset, input clear,
@@ -25,18 +25,20 @@ module packet_reframer
    output dst_rdy_o,
    output [18:0] data_o,
    output src_rdy_o,
-   input dst_rdy_i);
+   input dst_rdy_i,
+   output reg state,
+   output eof_out,
+   output reg [15:0] length);
 
-   reg [1:0] state;
-   reg [15:0] length;
+   //reg state;
+   //reg [15:0] length;
    
    localparam RF_IDLE = 0;
    localparam RF_PKT = 1;
-   localparam RF_DUMP = 2;
    
    always @(posedge clk)
      if(reset | clear)
-       state <= 0;
+       state <= RF_IDLE;
      else
        if(src_rdy_i & dst_rdy_i)
 	 case(state)
@@ -47,26 +49,16 @@ module packet_reframer
 	     end
 	   RF_PKT :
 	     begin
-		if(length == 2)
-		  if(data_i[17])
-		    state <= RF_IDLE;
-		  else
-		    state <= RF_DUMP;
-		else
-		  length <= length - 1;
+		if(eof_out) state <= RF_IDLE;
+		length <= length - 1;
 	     end
-	   RF_DUMP :
-	     if(data_i[17])
-	       state <= RF_IDLE;
-	   default :
-	     state<= RF_IDLE;
 	 endcase // case (state)
    
    assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok
-   assign src_rdy_o = src_rdy_i & (state != RF_DUMP);
+   assign src_rdy_o = src_rdy_i;
    
    wire occ_out = 0;
-   wire eof_out = (state == RF_PKT) & (length == 2);
+   assign eof_out = (state == RF_PKT) & (length == 2);
    wire sof_out = (state == RF_IDLE);
    wire [15:0] data_out = data_i[15:0];
    assign data_o = {occ_out, eof_out, sof_out, data_out};