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author | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
commit | 45c1af8152d02cd7d4e5d5d603e1cca65f6dd539 (patch) | |
tree | 2a48c592cef637476c2566fc64675dcdac8a7b05 /fpga/usrp2/gpif/fifo36_to_gpmc16.v | |
parent | 7a1824e8fddadd915e2d7490a8b57764b815b09f (diff) | |
parent | 295c7e7b98df98989f3fb4505e44f0be52813d81 (diff) | |
download | uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.gz uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.bz2 uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.zip |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/gpif/fifo36_to_gpmc16.v')
-rw-r--r-- | fpga/usrp2/gpif/fifo36_to_gpmc16.v | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/fpga/usrp2/gpif/fifo36_to_gpmc16.v b/fpga/usrp2/gpif/fifo36_to_gpmc16.v new file mode 100644 index 000000000..508cd319c --- /dev/null +++ b/fpga/usrp2/gpif/fifo36_to_gpmc16.v @@ -0,0 +1,54 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +module fifo36_to_gpmc16 +#( + parameter FIFO_SIZE = 9 +) +( + //input fifo interface + input fifo_clk, input fifo_rst, + input [35:0] in_data, + input in_src_rdy, + output in_dst_rdy, + + //output interface + input gpif_clk, input gpif_rst, + output [15:0] out_data, + output valid, + input enable, + output eof +); + + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk + (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(), + .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), + .arst(fifo_rst | gpif_rst)); + + wire [18:0] data18_int; + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), + .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .f19_dataout(data18_int), .f19_src_rdy_o(valid), .f19_dst_rdy_i(enable) ); + + assign out_data = data18_int[15:0]; + assign eof = data18_int[17]; + +endmodule //fifo_to_gpmc16 |