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| author | Philip Balister <philip@opensdr.com> | 2010-09-21 20:06:43 +0000 |
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| committer | Philip Balister <philip@opensdr.com> | 2010-09-21 20:06:43 +0000 |
| commit | 77cdb4a9695e71e64e1d87cfad2cb4d8717f971e (patch) | |
| tree | a3dc039b2c7124f988acda462d2aa76f5877f011 /fpga/usrp2/fifo | |
| parent | 943bfa271c97b36dcba74f1d65220e6f66f50c7f (diff) | |
| download | uhd-77cdb4a9695e71e64e1d87cfad2cb4d8717f971e.tar.gz uhd-77cdb4a9695e71e64e1d87cfad2cb4d8717f971e.tar.bz2 uhd-77cdb4a9695e71e64e1d87cfad2cb4d8717f971e.zip | |
Use a dummy write to start DMA transfers when sending data to the FPGA.
Poll will also start data transfers.
Diffstat (limited to 'fpga/usrp2/fifo')
0 files changed, 0 insertions, 0 deletions