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authorJosh Blum <josh@joshknows.com>2011-05-09 16:47:04 -0700
committerJosh Blum <josh@joshknows.com>2011-05-09 16:47:04 -0700
commit91e32eaea25b023ec33b0efc80a653dac5a676df (patch)
tree0b1841b9a95a8ff22e47ec48387decd4005ca8db /fpga/usrp2/fifo
parent9daf1f0a7be5f6a2cc220e0c2f746e65dc649568 (diff)
parentd8aae182ffdafdd61bbd0100f845d7c93e6ec591 (diff)
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Merge branch 'next' into use_vita_length
Diffstat (limited to 'fpga/usrp2/fifo')
-rw-r--r--fpga/usrp2/fifo/dsp_framer36.v16
1 files changed, 10 insertions, 6 deletions
diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v
index c2ae8f96c..58455cee1 100644
--- a/fpga/usrp2/fifo/dsp_framer36.v
+++ b/fpga/usrp2/fifo/dsp_framer36.v
@@ -1,9 +1,13 @@
-// Frame DSP packets with a header line to be handled by the protocol machine
+// This has 3 functions:
+// Correct the VITA packet length
+// [optional] Frame DSP packets with an header line to be handled by the protocol machine
+// Hold on to the packet until there is a complete one before allowing to leave
module dsp_framer36
#(parameter BUF_SIZE = 9,
- parameter PORT_SEL = 0)
+ parameter PORT_SEL = 0,
+ parameter PROT_ENG_FLAGS = 1)
(input clk, input reset, input clear,
input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
@@ -48,10 +52,10 @@ module dsp_framer36
always @(posedge clk)
if(reset | clear)
- pkt_len_out <= 0;
+ pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1);
else if(do_xfer_out)
if(dfifo_out_data[33]) // eof
- pkt_len_out <= 0;
+ pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1);
else
pkt_len_out <= pkt_len_out + 1;
@@ -59,8 +63,8 @@ module dsp_framer36
wire [1:0] port_sel_bits = PORT_SEL;
- assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} :
- (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} :
+ assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} :
+ (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} :
{dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] };
assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy;