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authorJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
committerJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
commit349d99c988b2eeb3d13d6229cbd4b80bc9f8153a (patch)
tree1c902bf9199f9f131987e6dec42156c56f481eea /fpga/usrp2/fifo/fifo_tb.v
parent55658336cf67810ab8cd7829b9a1fa86c8cd4539 (diff)
parentc174bf9acb2b2d142456f1186bd3e41e40d8a6d1 (diff)
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Merge branch 'features' into uhd_fpga_features
Conflicts: fpga/usrp2/vrt/vita_rx_control.v
Diffstat (limited to 'fpga/usrp2/fifo/fifo_tb.v')
-rw-r--r--fpga/usrp2/fifo/fifo_tb.v25
1 files changed, 22 insertions, 3 deletions
diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v
index f561df7fa..327da4700 100644
--- a/fpga/usrp2/fifo/fifo_tb.v
+++ b/fpga/usrp2/fifo/fifo_tb.v
@@ -24,20 +24,39 @@ module fifo_new_tb();
wire i1_sr, i1_dr;
wire i2_sr, i2_dr;
wire i3_sr, i3_dr;
+ wire i7_sr, i7_dr;
+
reg i4_dr = 0;
wire i4_sr;
- wire [35:0] i1, i4;
+ wire [35:0] i1, i4, i7;
wire [18:0] i2, i3;
wire [7:0] ll_data;
wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+ wire [35:0] err_dat;
+ wire err_src_rdy, err_dst_rdy;
+
+ reg trigger = 0;
+ initial #10000 trigger = 1;
fifo_short #(.WIDTH(36)) fifo_short1
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+ .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) );
+ gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp
+ (.clk(clk),.reset(rst),.clear(clear),
+ .trigger(trigger), .sent(),
+ .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940),
+ .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy));
+
+ fifo36_mux #(.prio(0)) fifo36_mux
+ (.clk(clk), .reset(rst), .clear(clear),
+ .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr),
+ .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy),
+ .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr));
+
fifo36_to_fifo19 fifo36_to_fifo19
(.clk(clk),.reset(rst),.clear(clear),
.f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
@@ -59,7 +78,7 @@ module fifo_new_tb();
(.clk(clk),.reset(rst),.clear(clear),
.f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
.f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
+
task ReadFromFIFO36;
begin
$display("Read from FIFO36");