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author | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
commit | f56c1247cbe7b7e90acee2711b5dda3356b9486a (patch) | |
tree | 81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/fifo/fifo_2clock_cascade.v | |
parent | 9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff) | |
parent | eb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff) | |
download | uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.gz uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.bz2 uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.zip |
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Diffstat (limited to 'fpga/usrp2/fifo/fifo_2clock_cascade.v')
-rw-r--r-- | fpga/usrp2/fifo/fifo_2clock_cascade.v | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/fpga/usrp2/fifo/fifo_2clock_cascade.v b/fpga/usrp2/fifo/fifo_2clock_cascade.v index 5ce726977..4e8c244c2 100644 --- a/fpga/usrp2/fifo/fifo_2clock_cascade.v +++ b/fpga/usrp2/fifo/fifo_2clock_cascade.v @@ -1,8 +1,10 @@ module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, + output [15:0] space, output [15:0] short_space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, + output [15:0] occupied, output [15:0] short_occupied, input arst); wire [WIDTH-1:0] data_int1, data_int2; @@ -29,7 +31,11 @@ module fifo_2clock_cascade .space(s2_space), .occupied(s2_occupied)); // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + + // For the fifo_extram, we only want to know the immediately adjacent space + assign short_space = {11'b0,s1_space}; + assign short_occupied = {11'b0,s2_occupied}; endmodule // fifo_2clock_cascade |