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authorJosh Blum <josh@joshknows.com>2010-10-14 16:55:56 -0700
committerJosh Blum <josh@joshknows.com>2010-10-14 16:55:56 -0700
commit26b7de0ac0cd64946582b2d52ab0bb3555156039 (patch)
tree5dc670eaaab60bf2bda90d905210bc9432cecea3 /fpga/usrp2/extramfifo
parent71e1763332141603e9edba097fd19b00e9a76ab8 (diff)
parentee03f1d4acf5c7d3359c86baba5085660d63ebae (diff)
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Merge branch 'flow_control' into flow_ctrl
Diffstat (limited to 'fpga/usrp2/extramfifo')
-rw-r--r--fpga/usrp2/extramfifo/.gitignore3
-rw-r--r--fpga/usrp2/extramfifo/Makefile.srcs16
-rw-r--r--fpga/usrp2/extramfifo/ext_fifo.v123
-rw-r--r--fpga/usrp2/extramfifo/ext_fifo_tb.cmd12
-rw-r--r--fpga/usrp2/extramfifo/ext_fifo_tb.prj9
-rw-r--r--fpga/usrp2/extramfifo/ext_fifo_tb.sh2
-rw-r--r--fpga/usrp2/extramfifo/ext_fifo_tb.v378
-rw-r--r--fpga/usrp2/extramfifo/fifo_extram.v188
-rw-r--r--fpga/usrp2/extramfifo/fifo_extram36.v47
-rwxr-xr-xfpga/usrp2/extramfifo/fifo_extram36_tb.build1
-rw-r--r--fpga/usrp2/extramfifo/fifo_extram36_tb.v475
-rwxr-xr-xfpga/usrp2/extramfifo/fifo_extram_tb.build1
-rw-r--r--fpga/usrp2/extramfifo/fifo_extram_tb.v134
-rw-r--r--fpga/usrp2/extramfifo/icon.v1286
-rw-r--r--fpga/usrp2/extramfifo/icon.xco47
-rw-r--r--fpga/usrp2/extramfifo/ila.v5544
-rw-r--r--fpga/usrp2/extramfifo/ila.xco130
-rw-r--r--fpga/usrp2/extramfifo/nobl_fifo.v96
-rw-r--r--fpga/usrp2/extramfifo/nobl_if.v139
-rw-r--r--fpga/usrp2/extramfifo/test_sram_if.v175
20 files changed, 8806 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/.gitignore b/fpga/usrp2/extramfifo/.gitignore
new file mode 100644
index 000000000..94bbf6dcc
--- /dev/null
+++ b/fpga/usrp2/extramfifo/.gitignore
@@ -0,0 +1,3 @@
+fifo_extram36_tb
+fifo_extram_tb
+*.vcd
diff --git a/fpga/usrp2/extramfifo/Makefile.srcs b/fpga/usrp2/extramfifo/Makefile.srcs
new file mode 100644
index 000000000..7cd49f4f6
--- /dev/null
+++ b/fpga/usrp2/extramfifo/Makefile.srcs
@@ -0,0 +1,16 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Extram Sources
+##################################################
+EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extramfifo/, \
+ext_fifo.v \
+nobl_if.v \
+nobl_fifo.v \
+icon.v \
+icon.xco \
+ila.v \
+ila.xco \
+))
diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v
new file mode 100644
index 000000000..2af59a75d
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo.v
@@ -0,0 +1,123 @@
+//
+// FIFO backed by an off chip ZBT/NoBL SRAM.
+//
+// This module and its sub-hierarchy implment a FIFO capable of sustaining
+// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits.
+//
+// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz,
+// your milage may vary with other clock ratio's especially those where int_clk < ext_clk.
+// Testing has also exclusively used a rst signal synchronized to int_clk.
+//
+// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through",
+// though signal naming differs.
+//
+// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be
+// packed into the IO ring.
+//
+
+ //`define NO_EXT_FIFO
+
+module ext_fifo
+ #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+ (
+ input int_clk,
+ input ext_clk,
+ input rst,
+ input [EXT_WIDTH-1:0] RAM_D_pi,
+ output [EXT_WIDTH-1:0] RAM_D_po,
+ output RAM_D_poe,
+ output [RAM_DEPTH-1:0] RAM_A,
+ output RAM_WEn,
+ output RAM_CENn,
+ output RAM_LDn,
+ output RAM_OEn,
+ output RAM_CE1n,
+ input [INT_WIDTH-1:0] datain,
+ input src_rdy_i, // WRITE
+ output dst_rdy_o, // not FULL
+ output [INT_WIDTH-1:0] dataout,
+ output src_rdy_o, // not EMPTY
+ input dst_rdy_i, // READ
+ output reg [31:0] debug,
+ output reg [31:0] debug2
+ );
+
+ wire [EXT_WIDTH-1:0] write_data;
+ wire [EXT_WIDTH-1:0] read_data;
+ wire full1, empty1;
+ wire almost_full2, full2, empty2;
+ wire [INT_WIDTH-1:0] data_to_fifo;
+ wire [INT_WIDTH-1:0] data_from_fifo;
+ wire [FIFO_DEPTH-1:0] capacity;
+
+
+ // FIFO buffers data from UDP engine into external FIFO clock domain.
+ fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
+ .rst(rst),
+ .wr_clk(int_clk),
+ .rd_clk(ext_clk),
+ .din(datain), // Bus [35 : 0]
+ .wr_en(src_rdy_i),
+ .rd_en(space_avail&~empty1),
+ .dout(write_data), // Bus [17 : 0]
+ .full(full1),
+ .empty(empty1));
+
+ assign dst_rdy_o = ~full1;
+
+`ifdef NO_EXT_FIFO
+ assign space_avail = ~full2;
+ assign data_avail = ~empty1;
+ assign read_data = write_data;
+`else
+
+ // External FIFO running at ext clock rate and 18 bit width.
+ nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH))
+ nobl_fifo_i1
+ (
+ .clk(ext_clk),
+ .rst(rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .write_data(write_data),
+ .write_strobe(~empty1 ),
+ .space_avail(space_avail),
+ .read_data(read_data),
+ .read_strobe(~almost_full2),
+ .data_avail(data_avail),
+ .capacity(capacity)
+ );
+`endif // !`ifdef NO_EXT_FIFO
+
+
+ // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+ fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
+ .rst(rst),
+ .wr_clk(ext_clk),
+ .rd_clk(int_clk),
+ .din(read_data), // Bus [17 : 0]
+ .wr_en(data_avail),
+ .rd_en(dst_rdy_i),
+ .dout(dataout), // Bus [35 : 0]
+ .full(full2),
+ .prog_full(almost_full2),
+ .empty(empty2));
+ assign src_rdy_o = ~empty2;
+
+ always @ (posedge int_clk)
+ debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
+
+ always @ (posedge ext_clk)
+ debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
+
+ always@ (posedge ext_clk)
+// debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+ debug2[31:0] <= 0;
+endmodule // ext_fifo
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd
new file mode 100644
index 000000000..521f88f21
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd
@@ -0,0 +1,12 @@
+/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v
+-y .
+-y ../coregen/
+-y ../fifo
+-y ../models
+-y /home/ianb/usrp-fpga/usrp2/sdr_lib
+-y /home/ianb/usrp-fpga/usrp2/control_lib
+-y /home/ianb/usrp-fpga/usrp2/models
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib
+
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.prj b/fpga/usrp2/extramfifo/ext_fifo_tb.prj
new file mode 100644
index 000000000..a11a15b2f
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo_tb.prj
@@ -0,0 +1,9 @@
+verilog work "./ext_fifo_tb.v"
+verilog work "./ext_fifo.v"
+verilog work "./nobl_fifo.v"
+verilog work "./nobl_if.v"
+verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v"
+verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v"
+verilog work "../models/CY7C1356C/cy1356.v"
+verilog work "../models/idt71v65603s150.v"
+verilog work "$XILINX/verilog/src/glbl.v"
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh
new file mode 100644
index 000000000..dcfede37a
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo_tb.sh
@@ -0,0 +1,2 @@
+#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb
+iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.v b/fpga/usrp2/extramfifo/ext_fifo_tb.v
new file mode 100644
index 000000000..0eda89769
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo_tb.v
@@ -0,0 +1,378 @@
+`timescale 1ns / 1ps
+`define INT_WIDTH 36
+`define EXT_WIDTH 18
+`define RAM_DEPTH 19
+`define FIFO_DEPTH 8
+`define DUMP_VCD_FULL
+
+module ext_fifo_tb();
+
+
+ reg int_clk;
+ reg ext_clk;
+ reg rst;
+
+
+
+ wire [`EXT_WIDTH-1:0] RAM_D_pi;
+ wire [`EXT_WIDTH-1:0] RAM_D_po;
+ wire [`EXT_WIDTH-1:0] RAM_D;
+ wire RAM_D_poe;
+ wire [`RAM_DEPTH-1:0] RAM_A;
+ wire RAM_WEn;
+ wire RAM_CENn;
+ wire RAM_LDn;
+ wire RAM_OEn;
+ wire RAM_CE1n;
+ reg [`INT_WIDTH-1:0] datain;
+ reg src_rdy_i; // WRITE
+ wire dst_rdy_o; // not FULL
+ wire [`INT_WIDTH-1:0] dataout;
+ reg [`INT_WIDTH-1:0] ref_dataout;
+ wire src_rdy_o; // not EMPTY
+ reg dst_rdy_i;
+ integer ether_frame;
+
+
+ // Clocks
+ // Int clock is 100MHz
+ // Ext clock is 125MHz
+ initial
+ begin
+ int_clk <= 0;
+ ext_clk <= 0;
+ ref_dataout <= 1;
+ src_rdy_i <= 0;
+ dst_rdy_i <= 0;
+ end
+
+ always
+ #5 int_clk <= ~int_clk;
+
+ always
+ #4 ext_clk <= ~ext_clk;
+
+ initial
+ begin
+ datain <= 0;
+ ether_frame <= 0;
+
+ rst <= 1;
+ repeat (5) @(negedge int_clk);
+ rst <= 0;
+ @(negedge int_clk);
+ while (datain < 10000)
+ begin
+ @(negedge int_clk);
+ datain <= datain + dst_rdy_o;
+ src_rdy_i <= dst_rdy_o;
+ // Simulate inter-frame time
+ if (ether_frame == 1500)
+ begin
+ ether_frame <= 0;
+ repeat(1600)
+ begin
+ @(negedge int_clk);
+ src_rdy_i <= 0;
+ end
+ end
+ else
+ ether_frame <= ether_frame + dst_rdy_o;
+ end
+ end // initial begin
+
+
+ initial
+ begin
+ repeat (5) @(negedge int_clk);
+ dst_rdy_i <= 1;
+
+ while (src_rdy_o !== 1)
+ @(negedge int_clk);
+
+ // Fall through fifo, first output already valid
+ if (dataout !== ref_dataout)
+ $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+
+ // Decimate by 16 rate
+ while (ref_dataout < 2000)
+ begin
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+ @(negedge int_clk);
+ dst_rdy_i <= 0;
+ repeat(14) @(negedge int_clk);
+ end // while (ref_dataout < 10000)
+ // Decimate by 8 rate
+ while (ref_dataout < 4000)
+ begin
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+ @(negedge int_clk);
+ dst_rdy_i <= 0;
+ repeat(6) @(negedge int_clk);
+ end // while (ref_dataout < 10000)
+ // Decimate by 4 rate
+ while (ref_dataout < 6000)
+ begin
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+ @(negedge int_clk);
+ dst_rdy_i <= 0;
+ repeat(2) @(negedge int_clk);
+ end // while (ref_dataout < 10000)
+ // Max rate
+ while (ref_dataout < 10000)
+ begin
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time);
+
+ end // while (ref_dataout < 10000)
+
+ @(negedge int_clk);
+ $finish;
+
+ end
+
+
+/* -----\/----- EXCLUDED -----\/-----
+
+ initial
+ begin
+ rst <= 1;
+ repeat (5) @(negedge int_clk);
+ rst <= 0;
+ @(negedge int_clk);
+ repeat (4000)
+ begin
+ @(negedge int_clk);
+ datain <= datain + dst_rdy_o;
+ src_rdy_i <= dst_rdy_o;
+// @(negedge int_clk);
+// src_rdy_i <= 0;
+// @(negedge int_clk);
+// dst_rdy_i <= src_rdy_o;
+// @(negedge int_clk);
+// dst_rdy_i <= 0;
+// repeat (2) @(negedge int_clk);
+ end // repeat (1000)
+ // Fall through fifo, first output already valid
+ if (dataout !== ref_dataout)
+ $display("Error: Expected %x, got %x",ref_dataout, dataout);
+ repeat (1000)
+ begin
+ @(negedge int_clk);
+ datain <= datain + dst_rdy_o ;
+ src_rdy_i <= dst_rdy_o;
+ @(negedge int_clk);
+ src_rdy_i <= 0;
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o ;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x",ref_dataout, dataout);
+ @(negedge int_clk);
+ dst_rdy_i <= 0;
+// repeat (2) @(negedge int_clk);
+ end // repeat (1000)
+ repeat (1000)
+ begin
+// @(negedge int_clk);
+// datain <= datain + 1;
+// src_rdy_i <= 1;
+// @(negedge int_clk);
+// src_rdy_i <= 0;
+ @(negedge int_clk);
+ ref_dataout <= ref_dataout + src_rdy_o;
+ dst_rdy_i <= src_rdy_o;
+ if ((dataout !== ref_dataout) && src_rdy_o)
+ $display("Error: Expected %x, got %x",ref_dataout, dataout);
+ @(negedge int_clk);
+ dst_rdy_i <= 0;
+// repeat (2) @(negedge int_clk);
+ end // repeat (1000)
+
+ $finish;
+
+ end // initial begin
+
+
+ -----/\----- EXCLUDED -----/\----- */
+ ///////////////////////////////////////////////////////////////////////////////////
+ // Simulation control //
+ ///////////////////////////////////////////////////////////////////////////////////
+ `ifdef DUMP_LX2_TOP
+ // Set up output files
+ initial begin
+ $dumpfile("ext_fifo_tb.lx2");
+ $dumpvars(1,ext_fifo_tb);
+ end
+ `endif
+
+ `ifdef DUMP_LX2_FULL
+ // Set up output files
+ initial begin
+ $dumpfile("ext_fifo_tb.lx2");
+ $dumpvars(0,ext_fifo_tb);
+ end
+ `endif
+
+ `ifdef DUMP_VCD_TOP
+ // Set up output files
+ initial begin
+ $dumpfile("ext_fifo_tb.vcd");
+ $dumpvars(1,ext_fifo_tb);
+ end
+ `endif
+
+ `ifdef DUMP_VCD_TOP_PLUS_NEXT
+ // Set up output files
+ initial begin
+ $dumpfile("ext_fifo_tb.vcd");
+ $dumpvars(2,ext_fifo_tb);
+ end
+ `endif
+
+
+ `ifdef DUMP_VCD_FULL
+ // Set up output files
+ initial begin
+ $dumpfile("ext_fifo_tb.vcd");
+ $dumpvars(0,ext_fifo_tb);
+ end
+ `endif
+
+ // Update display every 10 us
+ always #10000 $monitor("Time in uS ",$time/1000);
+
+ wire [`EXT_WIDTH-1:0] RAM_D_pi_ext;
+ wire [`EXT_WIDTH-1:0] RAM_D_po_ext;
+ wire [`EXT_WIDTH-1:0] RAM_D_ext;
+ wire RAM_D_poe_ext;
+
+ genvar i;
+
+ //
+ // Instantiate IO for Bidirectional bus to SRAM
+ //
+
+ generate
+ for (i=0;i<18;i=i+1)
+ begin : gen_RAM_D_IO
+
+ IOBUF #(
+ .DRIVE(12),
+ .IOSTANDARD("LVCMOS25"),
+ .SLEW("FAST")
+ )
+ RAM_D_i (
+ .O(RAM_D_pi_ext[i]),
+ .I(RAM_D_po_ext[i]),
+ .IO(RAM_D[i]),
+ .T(RAM_D_poe_ext)
+ );
+ end // block: gen_RAM_D_IO
+
+ endgenerate
+
+ wire [`RAM_DEPTH-1:0] RAM_A_ext;
+ wire RAM_WEn_ext,RAM_LDn_ext,RAM_CE1n_ext,RAM_OEn_ext,RAM_CENn_ext;
+
+ assign #1 RAM_D_pi = RAM_D_pi_ext;
+
+ assign #1 RAM_D_po_ext = RAM_D_po;
+
+ assign #1 RAM_D_poe_ext = RAM_D_poe;
+
+ assign #2 RAM_WEn_ext = RAM_WEn;
+
+ assign #2 RAM_LDn_ext = RAM_LDn;
+
+ assign #2 RAM_CE1n_ext = RAM_CE1n;
+
+ assign #2 RAM_OEn_ext = RAM_OEn;
+
+ assign #2 RAM_CENn_ext = RAM_CENn;
+
+ assign #2 RAM_A_ext = RAM_A;
+
+
+
+ idt71v65603s150 idt71v65603s150_i1
+ (
+ .A(RAM_A_ext[17:0]),
+ .adv_ld_(RAM_LDn_ext), // advance (high) / load (low)
+ .bw1_(1'b0),
+ .bw2_(1'b0),
+ .bw3_(1'b1),
+ .bw4_(1'b1), // byte write enables (low)
+ .ce1_(RAM_CE1n_ext),
+ .ce2(1'b1),
+ .ce2_(1'b0), // chip enables
+ .cen_(RAM_CENn_ext), // clock enable (low)
+ .clk(ext_clk), // clock
+ .IO({RAM_D[16:9],RAM_D[7:0]}),
+ .IOP({RAM_D[17],RAM_D[8]}), // data bus
+ .lbo_(1'b0), // linear burst order (low)
+ .oe_(RAM_OEn_ext), // output enable (low)
+ .r_w_(RAM_WEn_ext)
+ ); // read (high) / write (low)
+
+/* -----\/----- EXCLUDED -----\/-----
+
+
+ cy1356 cy1356_i1
+ ( .d(RAM_D),
+ .clk(ext_clk),
+ .a(RAM_A_ext),
+ .bws(2'b00),
+ .we_b(RAM_WEn_ext),
+ .adv_lb(RAM_LDn_ext),
+ .ce1b(RAM_CE1n_ext),
+ .ce2(1'b1),
+ .ce3b(1'b0),
+ .oeb(RAM_OEn_ext),
+ .cenb(RAM_CENn_ext),
+ .mode(1'b0)
+ );
+ -----/\----- EXCLUDED -----/\----- */
+
+
+ ext_fifo
+ #(.INT_WIDTH(`INT_WIDTH),.EXT_WIDTH(`EXT_WIDTH),.RAM_DEPTH(`RAM_DEPTH),.FIFO_DEPTH(`FIFO_DEPTH))
+ ext_fifo_i1
+ (
+ .int_clk(int_clk),
+ .ext_clk(ext_clk),
+ .rst(rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .datain(datain),
+ .src_rdy_i(src_rdy_i), // WRITE
+ .dst_rdy_o(dst_rdy_o), // not FULL
+ .dataout(dataout),
+ .src_rdy_o(src_rdy_o), // not EMPTY
+ .dst_rdy_i(dst_rdy_i)
+ );
+
+endmodule // ext_fifo_tb
diff --git a/fpga/usrp2/extramfifo/fifo_extram.v b/fpga/usrp2/extramfifo/fifo_extram.v
new file mode 100644
index 000000000..4e1f40371
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram.v
@@ -0,0 +1,188 @@
+
+// Everything on sram_clk
+
+module fifo_extram
+ (input reset, input clear,
+ input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in,
+ output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in,
+ input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we,
+ output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe,
+ output sram_mode, output sram_zz);
+
+ localparam AWIDTH = 19; // 1 MB in x18
+ localparam RAMSIZE = ((1<<AWIDTH) - 1);
+
+ wire do_store, do_retrieve;
+ reg [1:0] do_store_del, do_retr_del;
+
+ reg [AWIDTH-1:0] addr_retrieve, addr_store;
+ always @(posedge sram_clk)
+ if(reset | clear)
+ addr_retrieve <= 0;
+ else if (do_retrieve)
+ addr_retrieve <= addr_retrieve + 1;
+
+ always @(posedge sram_clk)
+ if(reset | clear)
+ addr_store <= 0;
+ else if(do_store)
+ addr_store <= addr_store + 1;
+
+ //wire [AWIDTH-1:0] fullness = (addr_store - addr_retrieve);
+ reg [AWIDTH-1:0] fullness;
+ always @(posedge sram_clk)
+ if(reset | clear)
+ fullness <= 0;
+ else if(do_store)
+ fullness <= fullness + 1;
+ else if(do_retrieve)
+ fullness <= fullness - 1;
+
+ // wire empty = (fullness == 0);
+ //wire full = (fullness == RAMSIZE); // 19'h7FF);
+ reg empty, full;
+
+ // The math in the following functions is 'AWIDTH wide. Use
+ // continuous assignments to prevent the numbers from being
+ // promoted to 32-bit (which would make it wrap wrong).
+ //
+ wire [AWIDTH-1:0] addr_retrieve_p1, addr_store_p2;
+ assign addr_retrieve_p1 = addr_retrieve + 1;
+ assign addr_store_p2 = addr_store + 2;
+
+ always @(posedge sram_clk)
+ if(reset | clear)
+ empty <= 1;
+ else if(do_store)
+ empty <= 0;
+ else if(do_retrieve & (/*(addr_retrieve + 1)*/ addr_retrieve_p1 == addr_store))
+ empty <= 1;
+
+ always @(posedge sram_clk)
+ if(reset | clear)
+ full <= 0;
+ else if(do_retrieve)
+ full <= 0;
+ else if(do_store & (/*(addr_store+2)*/ addr_store_p2 == addr_retrieve))
+ full <= 1;
+
+ reg can_store;
+ always @*
+ if(full | ~src_rdy_i)
+ can_store <= 0;
+ else if(do_store_del == 0)
+ can_store <= 1;
+ else if((do_store_del == 1) || (do_store_del == 2))
+ can_store <= (occ_in > 1);
+ else
+ can_store <= (occ_in > 2);
+
+ reg can_retrieve;
+ always @*
+ if(empty | ~dst_rdy_i)
+ can_retrieve <= 0;
+ else if(do_retr_del == 0)
+ can_retrieve <= 1;
+ else if((do_retr_del == 1) || (do_retr_del == 2))
+ can_retrieve <= (space_in > 1);
+ else
+ can_retrieve <= (space_in > 2);
+
+ reg [1:0] state;
+ localparam IDLE_STORE_NEXT = 0;
+ localparam STORE = 1;
+ localparam IDLE_RETR_NEXT = 2;
+ localparam RETRIEVE = 3;
+
+ reg [7:0] countdown;
+ wire countdown_done = (countdown == 0);
+
+ localparam CYCLE_SIZE = 6;
+
+ assign do_store = can_store & (state == STORE);
+ assign do_retrieve = can_retrieve & (state == RETRIEVE);
+ always @(posedge sram_clk)
+ if(reset)
+ do_store_del <= 0;
+ else
+ do_store_del <= {do_store_del[0],do_store};
+
+ always @(posedge sram_clk)
+ if(reset)
+ do_retr_del <= 0;
+ else
+ do_retr_del <= {do_retr_del[0],do_retrieve};
+
+ always @(posedge sram_clk)
+ if(reset | clear)
+ begin
+ state <= IDLE_STORE_NEXT;
+ countdown <= 0;
+ end
+ else
+ case(state)
+ IDLE_STORE_NEXT :
+ if(can_store)
+ begin
+ state <= STORE;
+ countdown <= CYCLE_SIZE;
+ end
+ else if(can_retrieve)
+ begin
+ state <= RETRIEVE;
+ countdown <= CYCLE_SIZE;
+ end
+ STORE :
+ if(~can_store | (can_retrieve & countdown_done))
+ state <= IDLE_RETR_NEXT;
+ else if(~countdown_done)
+ countdown <= countdown - 1;
+ IDLE_RETR_NEXT :
+ if(can_retrieve)
+ begin
+ state <= RETRIEVE;
+ countdown <= CYCLE_SIZE;
+ end
+ else if(can_store)
+ begin
+ state <= STORE;
+ countdown <= CYCLE_SIZE;
+ end
+ RETRIEVE :
+ if(~can_retrieve | (can_store & countdown_done))
+ state <= IDLE_STORE_NEXT;
+ else if(~countdown_done)
+ countdown <= countdown - 1;
+ endcase // case (state)
+
+ // RAM wires
+ assign sram_bw = 0;
+ assign sram_adv = 0;
+ assign sram_mode = 0;
+ assign sram_zz = 0;
+ assign sram_ce = 0;
+
+ assign sram_a = (state==STORE) ? addr_store : addr_retrieve;
+ assign sram_we = ~do_store;
+ assign sram_oe = ~do_retr_del[1];
+ assign my_oe = do_store_del[1] & sram_oe;
+ assign sram_d = my_oe ? datain : 18'bz;
+
+ // FIFO wires
+ assign dataout = sram_d;
+ assign src_rdy_o = do_retr_del[1];
+ assign dst_rdy_o = do_store_del[1];
+
+endmodule // fifo_extram
+
+
+ //wire have_1 = (fullness == 1);
+ //wire have_2 = (fullness == 2);
+ //wire have_atleast_1 = ~empty;
+ //wire have_atleast_2 = ~(empty | have_1);
+ //wire have_atleast_3 = ~(empty | have_1 | have_2);
+ //wire full_minus_1 = (fullness == (RAMSIZE-1)); // 19'h7FE);
+ //wire full_minus_2 = (fullness == (RAMSIZE-2)); // 19'h7FD);
+ //wire spacefor_atleast_1 = ~full;
+ //wire spacefor_atleast_2 = ~(full | full_minus_1);
+ //wire spacefor_atleast_3 = ~(full | full_minus_1 | full_minus_2);
diff --git a/fpga/usrp2/extramfifo/fifo_extram36.v b/fpga/usrp2/extramfifo/fifo_extram36.v
new file mode 100644
index 000000000..29342fdc4
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram36.v
@@ -0,0 +1,47 @@
+
+// 18 bit interface means we either can't handle errors or can't handle odd lengths
+// unless we go to heroic measures
+
+module fifo_extram36
+ (input clk, input reset, input clear,
+ input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we,
+ output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode,
+ output sram_zz);
+
+ wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4;
+ wire f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2;
+ wire f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4;
+
+ fifo36_to_fifo18 f36_to_f18
+ (.clk(clk), .reset(reset), .clear(clear),
+ .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
+ .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) );
+
+ wire [15:0] f1_occ, f2_space;
+
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in
+ (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(),
+ .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ),
+ .arst(reset) );
+
+ fifo_extram fifo_extram
+ (.reset(reset), .clear(clear),
+ .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ),
+ .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space),
+ .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
+ .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
+ .sram_mode(sram_mode), .sram_zz(sram_zz));
+
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out
+ (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space),
+ .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(),
+ .arst(reset) );
+
+ fifo18_to_fifo36 f18_to_f36
+ (.clk(clk), .reset(reset), .clear(clear),
+ .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4),
+ .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) );
+
+endmodule // fifo_extram36
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build
new file mode 100755
index 000000000..ac9369758
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.build
@@ -0,0 +1 @@
+iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.v b/fpga/usrp2/extramfifo/fifo_extram36_tb.v
new file mode 100644
index 000000000..e5f8cef4c
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.v
@@ -0,0 +1,475 @@
+`timescale 1ns/1ns
+
+module fifo_extram36_tb();
+
+ reg clk = 0;
+ reg sram_clk = 0;
+ reg rst = 1;
+ reg clear = 0;
+
+ reg Verbose = 0; //
+ integer ErrorCount = 0;
+
+ initial #1000 rst = 0;
+// always #125 clk = ~clk;
+ task task_CLK;
+ reg [7:0] ran;
+ begin
+ while (1) begin
+ ran = $random;
+ if (ran[1])
+ #62 clk = ~clk;
+ else
+ #63 clk = !clk;
+ end
+ end
+ endtask // task_CLK
+ initial task_CLK;
+
+// always #100 sram_clk = ~sram_clk;
+ task task_SSRAM_clk;
+ reg [7:0] ran;
+ begin
+ while (1) begin
+ ran = $random;
+ if (ran[0])
+ #49 sram_clk = ~sram_clk;
+ else
+ #51 sram_clk = ~sram_clk;
+ end
+ end
+ endtask // task_SSRAM_clk
+ initial task_SSRAM_clk;
+
+ reg [31:0] f36_data = 32'hX;
+ reg [1:0] f36_occ = 0;
+ reg f36_sof = 0, f36_eof = 0;
+
+ wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data};
+ reg src_rdy_f36i = 0;
+ wire dst_rdy_f36i;
+
+ wire [35:0] f36_out;
+ wire src_rdy_f36o;
+ reg dst_rdy_f36o = 0;
+
+ wire [17:0] sram_d;
+ wire [18:0] sram_a;
+ wire [1:0] sram_bw;
+ wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz;
+
+ reg [31:0] ScoreBoard [524288:0];
+ reg [18:0] put_index = 0;
+ reg [18:0] get_index = 0;
+
+// integer put_index = 0;
+// integer get_index = 0;
+
+ wire [15:0] DUT_space, DUT_occupied;
+
+ fifo_extram36 fifo_extram36
+ (.clk(clk), .reset(rst), .clear(clear),
+ .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space),
+ .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied),
+ .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
+ .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
+ .sram_mode(sram_mode), .sram_zz(sram_zz));
+
+`define idt 1
+`ifdef idt
+ wire [15:0] dummy16;
+ wire [1:0] dummy2;
+
+ idt71v65603s150
+ ram_model(.A(sram_a[17:0]),
+ .adv_ld_(sram_adv), // advance (high) / load (low)
+ .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low)
+ .ce1_(0), .ce2(1), .ce2_(0), // chip enables
+ .cen_(sram_ce), // clock enable (low)
+ .clk(sram_clk), // clock
+ .IO({dummy16,sram_d[15:0]}),
+ .IOP({dummy2,sram_d[17:16]}), // data bus
+ .lbo_(sram_mode), // linear burst order (low)
+ .oe_(sram_oe), // output enable (low)
+ .r_w_(sram_we)); // read (high) / write (low)
+`else
+ cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a),
+ .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv),
+ .ce1b(0),.ce2(1),.ce3b(0),
+ .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) );
+`endif
+
+ task task_SSRAMMonitor;
+ reg last_mode;
+ reg last_clock;
+ reg last_load;
+ reg [18:0] sram_addr;
+
+ begin
+ last_mode = 1'bX;
+ last_clock = 1'bX;
+ last_load = 1'bX;
+
+ @ (posedge Verbose);
+ $dumpvars(0,fifo_extram36_tb);
+
+ $display("%t:%m\t*** Task Started",$time);
+ while (1) @ (posedge sram_clk) begin
+ if (sram_mode !== last_mode) begin
+ $display("%t:%m\tSSRAM mode: %b",$time,sram_mode);
+ last_mode = sram_mode;
+ end
+ if (sram_adv !== last_load) begin
+ $display("%t:%m\tSSRAM adv/load: %b",$time,sram_adv);
+ last_load = sram_adv;
+ end
+ if (sram_ce !== last_clock) begin
+ $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce);
+ last_clock = sram_ce;
+ end
+ if (sram_ce == 1'b0) begin
+ if (sram_adv == 1'b0) begin
+// $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a);
+ sram_addr = sram_a;
+ end else begin
+ sram_addr = sram_addr + 1;
+ end
+ if (sram_oe == 1'b0) begin
+ $display("%t:%m\tSSRAM Read Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d);
+ end
+ if (sram_we == 1'b0) begin
+ $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d);
+ end
+ if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin
+ $display("%t:%m\t*** ERROR: _oe and _we both active",$time);
+ end
+
+ end // if (sram_ce == 1'b0)
+
+ end // always @ (posedge sram_clk)
+ end
+ endtask // task_SSRAMMonitor
+
+ task ReadFromFIFO36;
+ begin
+ $display("%t: Read from FIFO36",$time);
+ #1 dst_rdy_f36o <= 1;
+ while(1)
+ begin
+ while(~src_rdy_f36o)
+ @(posedge clk);
+ $display("%t: Read: %h>",$time,f36_out);
+ @(posedge clk);
+ end
+ end
+ endtask // ReadFromFIFO36
+
+ initial dst_rdy_f36o = 0;
+
+ task task_ReadFIFO36;
+ reg [7:0] ran;
+ begin
+ $display("%t:%m\t*** Task Started",$time);
+ while (1) begin
+ // Read on one of four clocks
+ #5 dst_rdy_f36o <= 1;
+ @(posedge clk);
+ if (src_rdy_f36o) begin
+ if (f36_out[31:0] != ScoreBoard[get_index]) begin
+ $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index);
+ ErrorCount = ErrorCount + 1;
+ end else begin
+ if (Verbose)
+ $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out);
+ end
+ get_index = get_index+1;
+ end else begin
+ if (ErrorCount >= 192)
+ $finish;
+ end // else: !if(src_rdy_f36o)
+
+ #10;
+ ran = $random;
+ if (ran[2:0] != 3'b000) begin
+ dst_rdy_f36o <= 0;
+ if (ran[2] != 1'b0) begin
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ end
+ if (ran[1] != 1'b0) begin
+ @(posedge clk);
+ @(posedge clk);
+ end
+ if (ran[0] != 1'b0) begin
+ @(posedge clk);
+ end
+ end
+ end // while (1)
+ end
+
+ endtask // task_ReadFIFO36
+
+
+ reg [15:0] count;
+
+ task PutPacketInFIFO36;
+ input [31:0] data_start;
+ input [31:0] data_len;
+
+ begin
+ count = 4;
+ src_rdy_f36i = 1;
+ f36_data = data_start;
+ f36_sof = 1;
+ f36_eof = 0;
+ f36_occ = 0;
+
+ $display("%t: Put Packet in FIFO36",$time);
+ while(~dst_rdy_f36i)
+ #1; //@(posedge clk);
+ @(posedge clk);
+
+ $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data);
+ f36_sof <= 0;
+ while(count+4 < data_len)
+ begin
+ f36_data = f36_data + 32'h01010101;
+ count = count + 4;
+ while(~dst_rdy_f36i)
+ #1; //@(posedge clk);
+ @(posedge clk);
+ $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data);
+ end
+ f36_data <= f36_data + 32'h01010101;
+ f36_eof <= 1;
+ if(count + 4 == data_len)
+ f36_occ <= 0;
+ else if(count + 3 == data_len)
+ f36_occ <= 3;
+ else if(count + 2 == data_len)
+ f36_occ <= 2;
+ else
+ f36_occ <= 1;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ f36_occ <= 0;
+ f36_eof <= 0;
+ f36_data <= 0;
+ src_rdy_f36i <= 0;
+ $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data);
+ end
+ endtask // PutPacketInFIFO36
+
+ task task_WriteFIFO36;
+ integer i;
+ reg [7:0] ran;
+
+ begin
+ f36_data = 32'bX;
+ if (rst != 1'b0)
+ @ (negedge rst);
+ $display("%t:%m\t*** Task Started",$time);
+ #10;
+ src_rdy_f36i = 1;
+ f36_data = $random;
+ for (i=0; i<64; i=i+0 ) begin
+ @ (posedge clk) ;
+ if (dst_rdy_f36i) begin
+ if (Verbose)
+ $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in);
+ ScoreBoard[put_index] = f36_in[31:0];
+ put_index = put_index + 1;
+ #5;
+ f36_data = $random;
+ i = i + 1;
+ end
+ ran = $random;
+ if (ran[1:0] != 2'b00) begin
+ @ (negedge clk);
+ src_rdy_f36i = 0;
+ #5;
+ @ (negedge clk) ;
+ src_rdy_f36i = 1;
+ end
+ end
+ src_rdy_f36i = 0;
+ f36_data = 32'bX;
+// if (put_index > 19'h3ff00)
+// Verbose = 1'b1;
+
+ end
+ endtask // task_WriteFIFO36
+
+ initial $dumpfile("fifo_extram36_tb.vcd");
+// initial $dumpvars(0,fifo_extram36_tb);
+ initial $timeformat(-9, 0, " ns", 10);
+ initial task_SSRAMMonitor;
+
+ initial
+ begin
+ @(negedge rst);
+ #40000;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+// ReadFromFIFO36;
+ task_ReadFIFO36;
+
+ end
+
+ integer i;
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ task_WriteFIFO36;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+// PutPacketInFIFO36(32'hA0B0C0D0,12);
+ @(posedge clk);
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+// PutPacketInFIFO36(32'hE0F0A0B0,36);
+ @(posedge clk);
+ @(posedge clk);
+ task_WriteFIFO36;
+ @(posedge clk);
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+ @(posedge clk);
+ task_WriteFIFO36;
+// @(posedge clk);
+// #30000;
+// @(posedge clk);
+// @(posedge clk);
+ task_WriteFIFO36;
+// @(posedge clk);
+// #30000;
+// @(posedge clk);
+// @(posedge clk);
+ task_WriteFIFO36;
+// @(posedge clk);
+// #30000;
+// @(posedge clk);
+// @(posedge clk);
+ task_WriteFIFO36;
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+ @(posedge clk);
+ task_WriteFIFO36;
+ for (i=0; i<8192; i = i+1) begin
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+ @(posedge clk);
+ task_WriteFIFO36;
+ @(posedge clk);
+ end
+
+// $dumpvars(0,fifo_extram36_tb);
+ @(posedge clk);
+ task_WriteFIFO36;
+ @(posedge clk);
+
+ #100000000;
+ $finish;
+
+ end
+
+
+ initial
+ begin
+ @(negedge rst);
+ f36_occ <= 0;
+ repeat (100)
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= 32'h10203040;
+ f36_sof <= 1;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= f36_data + 32'h01010101;
+ f36_sof <= 0;
+ f36_eof <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 1;
+ f36_data <= 32'h1F2F3F4F;
+ f36_sof <= 0;
+ f36_eof <= 1;
+ @(posedge clk);
+ @(posedge clk);
+ src_rdy_f36i <= 0;
+
+
+
+ end
+
+// initial #500000 $finish;
+endmodule // fifo_extram_tb
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build
new file mode 100755
index 000000000..5607c8691
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram_tb.build
@@ -0,0 +1 @@
+iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.v b/fpga/usrp2/extramfifo/fifo_extram_tb.v
new file mode 100644
index 000000000..73550d9ca
--- /dev/null
+++ b/fpga/usrp2/extramfifo/fifo_extram_tb.v
@@ -0,0 +1,134 @@
+module fifo_extram_tb();
+
+ reg clk = 0;
+ reg sram_clk = 0;
+ reg reset = 1;
+ reg clear = 0;
+
+ initial #1000 reset = 0;
+ always #125 clk = ~clk;
+ always #100 sram_clk = ~sram_clk;
+
+ reg [15:0] f18_data = 0;
+ reg f18_sof = 0, f18_eof = 0;
+
+ wire [17:0] f18_in = {f18_eof,f18_sof,f18_data};
+ reg src_rdy_f18i = 0;
+ wire dst_rdy_f18i;
+
+ wire [17:0] f18_out;
+ wire src_rdy_f18o;
+ reg dst_rdy_f18o = 0;
+
+ wire [17:0] f18_int;
+ wire src_rdy_f18int, dst_rdy_f18int;
+
+ wire [17:0] sram_d;
+ wire [18:0] sram_a;
+ wire [1:0] sram_bw;
+ wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz;
+ wire [15:0] f1_occ;
+
+ fifo_short #(.WIDTH(18)) fifo_short
+ (.clk(sram_clk), .reset(reset), .clear(clear),
+ .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(),
+ .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) );
+
+ assign f1_occ[15:5] = 0;
+
+ fifo_extram fifo_extram
+ (.reset(reset), .clear(clear),
+ .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ),
+ .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7),
+ .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
+ .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
+ .sram_mode(sram_mode), .sram_zz(sram_zz));
+
+`define idt 1
+`ifdef idt
+ wire [15:0] dummy16;
+ wire [1:0] dummy2;
+
+ idt71v65603s150
+ ram_model(.A(sram_a[17:0]),
+ .adv_ld_(sram_adv), // advance (high) / load (low)
+ .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low)
+ .ce1_(0), .ce2(1), .ce2_(0), // chip enables
+ .cen_(sram_ce), // clock enable (low)
+ .clk(sram_clk), // clock
+ .IO({dummy16,sram_d[15:0]}),
+ .IOP({dummy2,sram_d[17:16]}), // data bus
+ .lbo_(sram_mode), // linear burst order (low)
+ .oe_(sram_oe), // output enable (low)
+ .r_w_(sram_we)); // read (high) / write (low)
+`else
+ cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a),
+ .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv),
+ .ce1b(0),.ce2(1),.ce3b(0),
+ .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) );
+`endif // !`ifdef idt
+
+ always @(posedge sram_clk)
+ if(dst_rdy_f18o & src_rdy_f18o)
+ $display("Read: %h",f18_out);
+
+ always @(posedge sram_clk)
+ if(dst_rdy_f18int & src_rdy_f18int)
+ $display("Write: %h",f18_int);
+
+ initial $dumpfile("fifo_extram_tb.vcd");
+ initial $dumpvars(0,fifo_extram_tb);
+
+ task SendPkt;
+ input [15:0] data_start;
+ input [31:0] data_len;
+ begin
+ @(posedge sram_clk);
+ f18_data = data_start;
+ f18_sof = 1;
+ f18_eof = 0;
+ src_rdy_f18i = 1;
+ while(~dst_rdy_f18i)
+ #1;
+ @(posedge sram_clk);
+ repeat(data_len - 2)
+ begin
+ f18_data = f18_data + 16'h0101;
+ f18_sof = 0;
+ while(~dst_rdy_f18i)
+ @(posedge sram_clk);
+
+ @(posedge sram_clk);
+ end
+ f18_data = f18_data + 16'h0101;
+ f18_eof = 1;
+ while(~dst_rdy_f18i)
+ #1;
+ @(posedge sram_clk);
+ src_rdy_f18i = 0;
+ f18_data = 0;
+ f18_eof = 0;
+ end
+ endtask // SendPkt
+
+ initial
+ begin
+ @(negedge reset);
+ @(posedge sram_clk);
+ @(posedge sram_clk);
+ #10000;
+ @(posedge sram_clk);
+ SendPkt(16'hA0B0, 100);
+ #10000;
+ //SendPkt(16'hC0D0, 220);
+ end
+
+ initial
+ begin
+ #20000;
+ dst_rdy_f18o = 1;
+ end
+
+ initial #200000 $finish;
+endmodule // fifo_extram_tb
+
diff --git a/fpga/usrp2/extramfifo/icon.v b/fpga/usrp2/extramfifo/icon.v
new file mode 100644
index 000000000..6537e9340
--- /dev/null
+++ b/fpga/usrp2/extramfifo/icon.v
@@ -0,0 +1,1286 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.53d
+// \ \ Application: netgen
+// / / Filename: icon.v
+// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v
+// Device : xc3s2000-fg456-5
+// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc
+// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v
+// # of Modules : 1
+// Design Name : icon
+// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module icon (
+CONTROL0
+)/* synthesis syn_black_box syn_noprune=1 */;
+ inout [35 : 0] CONTROL0;
+
+ // synthesis translate_off
+
+ wire N1;
+ wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ;
+ wire \U0/U_ICON/U_CMD/iSEL_n ;
+ wire \U0/U_ICON/U_CMD/iTARGET_CE ;
+ wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ;
+ wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ;
+ wire \U0/U_ICON/U_STAT/iDATA_VALID ;
+ wire \U0/U_ICON/U_STAT/iSTATCMD_CE ;
+ wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ;
+ wire \U0/U_ICON/U_STAT/iSTAT_HIGH ;
+ wire \U0/U_ICON/U_STAT/iSTAT_LOW ;
+ wire \U0/U_ICON/U_STAT/iTDO_next ;
+ wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ;
+ wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ;
+ wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ;
+ wire \U0/U_ICON/iCORE_ID_SEL[0] ;
+ wire \U0/U_ICON/iCORE_ID_SEL[15] ;
+ wire \U0/U_ICON/iDATA_CMD ;
+ wire \U0/U_ICON/iDATA_CMD_n ;
+ wire \U0/U_ICON/iSEL ;
+ wire \U0/U_ICON/iSEL_n ;
+ wire \U0/U_ICON/iSYNC ;
+ wire \U0/U_ICON/iTDI ;
+ wire \U0/U_ICON/iTDO ;
+ wire \U0/U_ICON/iTDO_next ;
+ wire \U0/iSHIFT_OUT ;
+ wire \U0/iUPDATE_OUT ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ;
+ wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ;
+ wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ;
+ wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ;
+ wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ;
+ wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ;
+ wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ;
+ wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ;
+ wire [3 : 0] \U0/U_ICON/iCORE_ID ;
+ wire [15 : 15] \U0/U_ICON/iTDO_VEC ;
+ GND XST_GND (
+ .G(CONTROL0[2])
+ );
+ VCC XST_VCC (
+ .P(N1)
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_TDI_reg (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/iTDI ),
+ .Q(CONTROL0[1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_TDO_reg (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/iTDO_next ),
+ .Q(\U0/U_ICON/iTDO )
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_iDATA_CMD (
+ .C(\U0/iUPDATE_OUT ),
+ .CLR(\U0/U_ICON/iSEL_n ),
+ .D(\U0/U_ICON/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/iDATA_CMD )
+ );
+ MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 (
+ .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ),
+ .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ),
+ .S(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iTDO_next )
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 (
+ .I0(CONTROL0[3]),
+ .I1(\U0/U_ICON/iCORE_ID [0]),
+ .I2(\U0/U_ICON/iCORE_ID [1]),
+ .I3(\U0/U_ICON/iCORE_ID [2]),
+ .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 (
+ .I0(\U0/U_ICON/iTDO_VEC [15]),
+ .I1(\U0/U_ICON/iCORE_ID [0]),
+ .I2(\U0/U_ICON/iCORE_ID [1]),
+ .I3(\U0/U_ICON/iCORE_ID [2]),
+ .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 )
+ );
+ INV \U0/U_ICON/U_iSEL_n (
+ .I(\U0/U_ICON/iSEL ),
+ .O(\U0/U_ICON/iSEL_n )
+ );
+ INV \U0/U_ICON/U_iDATA_CMD_n (
+ .I(\U0/U_ICON/iDATA_CMD ),
+ .O(\U0/U_ICON/iDATA_CMD_n )
+ );
+ BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS (
+ .TDI(\U0/U_ICON/iTDI ),
+ .SHIFT(\U0/iSHIFT_OUT ),
+ .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ),
+ .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ),
+ .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ),
+ .UPDATE(\U0/iUPDATE_OUT ),
+ .TDO1(\U0/U_ICON/iTDO ),
+ .TDO2(CONTROL0[2]),
+ .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ),
+ .SEL1(\U0/U_ICON/iSEL ),
+ .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED )
+ );
+ icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG (
+ .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ),
+ .DRCK_LOCAL_O(CONTROL0[0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC (
+ .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ),
+ .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC )
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC_L (
+ .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]),
+ .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]),
+ .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]),
+ .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW )
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC_H (
+ .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]),
+ .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]),
+ .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]),
+ .I3(CONTROL0[1]),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH )
+ );
+ INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n (
+ .I(\U0/U_ICON/iDATA_CMD ),
+ .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/U_SYNC (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ),
+ .D(N1),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/iSYNC )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(CONTROL0[1]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[20])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[4])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [1]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[21])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [1]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[5])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [2]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[22])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [2]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [3]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[23])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [3]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[7])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [4]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[24])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [4]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[8])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [5]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[25])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [5]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[9])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [6]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[26])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [6]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[10])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [7]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[27])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [7]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[11])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [8]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[28])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [8]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[12])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [9]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[29])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [9]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[13])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [10]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[30])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [10]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[14])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [11]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[31])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [11]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[15])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [12]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[32])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [12]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[16])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [13]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[33])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [13]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[17])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [14]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[34])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [14]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[18])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [15]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[35])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [15]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[19])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h1 ))
+ \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID (
+ .I0(\U0/U_ICON/iSYNC ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iCORE_ID_SEL[0] )
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0008 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0010 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0020 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0040 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0080 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0100 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0800 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h1000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h2000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h4000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iCORE_ID_SEL[15] )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [0])
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h0008 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h0010 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [4])
+ );
+ LUT4 #(
+ .INIT ( 16'h0020 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h0040 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h0080 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h0100 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [8])
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [9])
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [10])
+ );
+ LUT4 #(
+ .INIT ( 16'h0800 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [11])
+ );
+ LUT4 #(
+ .INIT ( 16'h1000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [12])
+ );
+ LUT4 #(
+ .INIT ( 16'h2000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [13])
+ );
+ LUT4 #(
+ .INIT ( 16'h4000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [14])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [15])
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/U_ICON/U_CMD/U_TARGET_CE (
+ .I0(\U0/U_ICON/iDATA_CMD ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_CMD/iTARGET_CE )
+ );
+ INV \U0/U_ICON/U_CMD/U_SEL_n (
+ .I(\U0/U_ICON/iSEL ),
+ .O(\U0/U_ICON/U_CMD/iSEL_n )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .Q(\U0/U_ICON/iCOMMAND_GRP [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .Q(\U0/U_ICON/iCOMMAND_GRP [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [0]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [1]),
+ .Q(\U0/U_ICON/iCORE_ID [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [2]),
+ .Q(\U0/U_ICON/iCORE_ID [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [3]),
+ .Q(\U0/U_ICON/iCORE_ID [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(CONTROL0[1]),
+ .Q(\U0/U_ICON/iCORE_ID [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0])
+ );
+ MUXF6 \U0/U_ICON/U_STAT/U_TDO_next (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/U_ICON/U_STAT/iTDO_next )
+ );
+ MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW (
+ .I0(\U0/U_ICON/U_STAT/iSTAT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT [1]),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/iSTAT_LOW )
+ );
+ MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH (
+ .I0(\U0/U_ICON/U_STAT/iSTAT [2]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT [3]),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/iSTAT_HIGH )
+ );
+ LUT4 #(
+ .INIT ( 16'h0101 ))
+ \U0/U_ICON/U_STAT/F_STAT[0].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [0])
+ );
+ LUT4 #(
+ .INIT ( 16'hC101 ))
+ \U0/U_ICON/U_STAT/F_STAT[1].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h2100 ))
+ \U0/U_ICON/U_STAT/F_STAT[2].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h1610 ))
+ \U0/U_ICON/U_STAT/F_STAT[3].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [3])
+ );
+ INV \U0/U_ICON/U_STAT/U_STATCMD_n (
+ .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ),
+ .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_STAT/U_STATCMD (
+ .I0(\U0/U_ICON/U_STAT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[15] ),
+ .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ),
+ .O(\U0/U_ICON/U_STAT/iSTATCMD_CE )
+ );
+ LUT2 #(
+ .INIT ( 4'h1 ))
+ \U0/U_ICON/U_STAT/U_CMDGRP0 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL )
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_STAT/U_DATA_VALID (
+ .I0(\U0/U_ICON/iSYNC ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_STAT/iDATA_VALID )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_TDO (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/iTDO_next ),
+ .Q(\U0/U_ICON/iTDO_VEC [15])
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/fpga/usrp2/extramfifo/icon.xco b/fpga/usrp2/extramfifo/icon.xco
new file mode 100644
index 000000000..fda273149
--- /dev/null
+++ b/fpga/usrp2/extramfifo/icon.xco
@@ -0,0 +1,47 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Wed Jul 21 03:31:19 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET enable_jtag_bufg=true
+CSET number_control_ports=1
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE
+# CRC: 799ba5a1
diff --git a/fpga/usrp2/extramfifo/ila.v b/fpga/usrp2/extramfifo/ila.v
new file mode 100644
index 000000000..b0d8f8d0c
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ila.v
@@ -0,0 +1,5544 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.53d
+// \ \ Application: netgen
+// / / Filename: ila.v
+// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v
+// Device : xc3s2000-fg456-5
+// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc
+// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v
+// # of Modules : 1
+// Design Name : ila
+// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module ila (
+ CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input CLK;
+ inout [35 : 0] CONTROL;
+ input [7 : 0] TRIG0;
+ input [7 : 0] TRIG1;
+ input [7 : 0] TRIG2;
+ input [3 : 0] TRIG3;
+
+ // synthesis translate_off
+
+ wire N0;
+ wire N1;
+ wire N38;
+ wire N39;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ;
+ wire \U0/I_NO_D.U_ILA/U_RST/POR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ;
+ wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ;
+ wire \U0/I_NO_D.U_ILA/iARM ;
+ wire \U0/I_NO_D.U_ILA/iCAPTURE ;
+ wire \U0/I_NO_D.U_ILA/iCAP_DONE ;
+ wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ;
+ wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ;
+ wire \U0/I_NO_D.U_ILA/iDATA_DOUT ;
+ wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ;
+ wire \U0/I_NO_D.U_ILA/iTRIGGER ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ;
+ wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ;
+ wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ;
+ wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ;
+ wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ;
+ wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ;
+ wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ;
+ wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ;
+ wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ;
+ wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ;
+ wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ;
+ wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ;
+ wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ;
+ wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ;
+ wire [27 : 0] \U0/iTRIG_IN ;
+ GND XST_GND (
+ .G(N0)
+ );
+ VCC XST_VCC (
+ .P(N1)
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [7]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [7]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1])
+ );
+ LUT3 #(
+ .INIT ( 8'h20 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG (
+ .I0(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0])
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0])
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]),
+ .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ),
+ .R(N0),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_DONE )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED )
+,
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED )
+,
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0])
+ );
+ SRL16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_CR (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0])
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_ARM (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_FULL (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .S(\U0/I_NO_D.U_ILA/iCAP_DONE ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_ECR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .S(N1),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/iARM ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .PRE(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 )
+ );
+ LDC #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (
+ .CLR(\U0/I_NO_D.U_ILA/iARM ),
+ .D(N1),
+ .G(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RISING (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ),
+ .D(N1),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_TDO (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ),
+ .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[5]),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(CONTROL[5]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT (
+ .C(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(CONTROL[5]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 )
+ );
+ LUT4 #(
+ .INIT ( 16'h5140 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 )
+ );
+ LUT2 #(
+ .INIT ( 4'hD ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFBEA ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 )
+ );
+ MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 )
+ );
+ LUT2 #(
+ .INIT ( 4'hE ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD (
+ .I0(CONTROL[4]),
+ .I1(CONTROL[5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE )
+ );
+ INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n (
+ .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSR (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0F22 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_NSL (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ),
+ .I3(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load )
+ );
+ LUT4 #(
+ .INIT ( 16'h0030 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16])
+ );
+ LUT4 #(
+ .INIT ( 16'h1030 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14])
+ );
+ LUT4 #(
+ .INIT ( 16'h1020 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12])
+ );
+ LUT4 #(
+ .INIT ( 16'h1010 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10])
+ );
+ LUT4 #(
+ .INIT ( 16'h100F ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9])
+ );
+ LUT4 #(
+ .INIT ( 16'hFFF0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8])
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h3000 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h001F ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5])
+ );
+ LUT4 #(
+ .INIT ( 16'hF001 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4])
+ );
+ LUT4 #(
+ .INIT ( 16'hB610 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h2100 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2])
+ );
+ LUT4 #(
+ .INIT ( 16'hC102 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h0101 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]),
+ .I1(CONTROL[5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_POR (
+ .C(CLK),
+ .D(N0),
+ .PRE(N0),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/POR )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [0])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [1])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [2])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [3])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [4])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [5])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [5]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [6])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hEF ))
+ \U0/I_NO_D.U_ILA/U_RST/U_PRST1 (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ),
+ .I1(\U0/I_NO_D.U_ILA/U_RST/POR ),
+ .I2(N1),
+ .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFFFE ))
+ \U0/I_NO_D.U_ILA/U_RST/U_PRST0 (
+ .I0(N0),
+ .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ),
+ .I2(N0),
+ .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ),
+ .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_RST0 (
+ .I0(\U0/I_NO_D.U_ILA/iARM ),
+ .I1(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ),
+ .I1(CONTROL[13]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[13]),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ),
+ .I1(CONTROL[12]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ),
+ .Q(\U0/I_NO_D.U_ILA/iARM )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[12]),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(CONTROL[12]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [24]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [25]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [26]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [27]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[23]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[23]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [0]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [1]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [2]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [3]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [4]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [5]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [6]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [7]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[20]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[20]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [8]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [9]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [10]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [11]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [12]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [13]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [14]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [15]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[21]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[21]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [16]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [17]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [18]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [19]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [20]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [21]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [22]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [23]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[22]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[22]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [0])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [1])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [2])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [3])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [4])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [5])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [6])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [7])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [8])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [9])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [10])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [11])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [12])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [13])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [14])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [15])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [16])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [17])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [18])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [19])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [20])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [21])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [22])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [23])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [24])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [25])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [26])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [27])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [0]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [1]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [2]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [3]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [4]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [5]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [6]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [7]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [8]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [9]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [10]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [11]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [12]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [13]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [14]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [15]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [16]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [17]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [18]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [19]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [20]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [21]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [22]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [23]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [24]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [25]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [26]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [27]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_DOUT (
+ .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ),
+ .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ),
+ .I2(CONTROL[6]),
+ .O(CONTROL[3])
+ );
+ LUT1 #(
+ .INIT ( 2'h1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B (
+ .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ),
+ .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]),
+ .CE(CONTROL[8]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED )
+
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]),
+ .I1(CONTROL[8]),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]),
+ .CE(CONTROL[8]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(CONTROL[1]),
+ .I1(CONTROL[8]),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/iCAPTURE )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [5]),
+ .Q(\U0/I_NO_D.U_ILA/iTRIGGER )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG3[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [27])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG3[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [26])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG3[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [25])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG3[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [24])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG2[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [23])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG2[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [22])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG2[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [21])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG2[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [20])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG2[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [19])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG2[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [18])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG2[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [17])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG2[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [16])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG1[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [15])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG1[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [14])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG1[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [13])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG1[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [12])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG1[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [11])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG1[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [10])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG1[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [9])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG1[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [8])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG0[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [7])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG0[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [6])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG0[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [5])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG0[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [4])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG0[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [3])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG0[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [2])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG0[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG0[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> (
+ .I0(CONTROL[10]),
+ .I1(CONTROL[11]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> (
+ .I0(CONTROL[12]),
+ .I1(CONTROL[13]),
+ .I2(CONTROL[9]),
+ .I3(CONTROL[14]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> (
+ .I0(CONTROL[15]),
+ .I1(CONTROL[16]),
+ .I2(CONTROL[8]),
+ .I3(CONTROL[17]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> (
+ .I0(CONTROL[18]),
+ .I1(CONTROL[21]),
+ .I2(CONTROL[7]),
+ .I3(CONTROL[19]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> (
+ .I0(CONTROL[20]),
+ .I1(CONTROL[22]),
+ .I2(CONTROL[6]),
+ .I3(CONTROL[23]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> (
+ .I0(CONTROL[24]),
+ .I1(CONTROL[25]),
+ .I2(CONTROL[5]),
+ .I3(CONTROL[26]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> (
+ .I0(CONTROL[27]),
+ .I1(CONTROL[28]),
+ .I2(CONTROL[2]),
+ .I3(CONTROL[29]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> (
+ .I0(CONTROL[30]),
+ .I1(CONTROL[31]),
+ .I2(CONTROL[1]),
+ .I3(CONTROL[32]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> (
+ .I0(CONTROL[33]),
+ .I1(CONTROL[34]),
+ .I2(CONTROL[4]),
+ .I3(CONTROL[35]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8])
+ );
+ LUT4 #(
+ .INIT ( 16'hFEFF ))
+ \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFFFE ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 )
+ );
+ LUT4 #(
+ .INIT ( 16'hF222 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ),
+ .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 )
+ );
+ LUT4 #(
+ .INIT ( 16'hAF8D ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 (
+ .I0(CONTROL[4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 (
+ .I0(N38),
+ .I1(N39),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 )
+ );
+ LUT3 #(
+ .INIT ( 8'h15 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .O(N38)
+ );
+ LUT4 #(
+ .INIT ( 16'h0145 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ),
+ .O(N39)
+ );
+ LUT4_L #(
+ .INIT ( 16'h3F50 ))
+ \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h3120 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 )
+ );
+ RAMB16_S1_S36 #(
+ .INIT_B ( 36'h000000000 ),
+ .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_A ( 1'h0 ),
+ .SIM_COLLISION_CHECK ( "ALL" ),
+ .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .SRVAL_A ( 1'h0 ),
+ .WRITE_MODE_A ( "WRITE_FIRST" ),
+ .WRITE_MODE_B ( "WRITE_FIRST" ),
+ .SRVAL_B ( 36'h000000000 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i (
+ .CLKA(CONTROL[0]),
+ .CLKB(CLK),
+ .ENA(CONTROL[6]),
+ .ENB(N1),
+ .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ),
+ .SSRA(N0),
+ .SSRB(N0),
+ .WEA(N0),
+ .DIPB({N0, N0, N0, N0}),
+ .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}),
+ .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]
+, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1],
+\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}),
+ .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24],
+\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19],
+\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14],
+\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9],
+\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4],
+\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }),
+ .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }),
+ .DIA({N0}),
+ .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }),
+ .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/fpga/usrp2/extramfifo/ila.xco b/fpga/usrp2/extramfifo/ila.xco
new file mode 100644
index 000000000..c8d4d2f75
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ila.xco
@@ -0,0 +1,130 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Wed Jul 21 18:51:14 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=0
+CSET data_same_as_trigger=true
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=false
+CSET exclude_from_data_storage_10=false
+CSET exclude_from_data_storage_11=false
+CSET exclude_from_data_storage_12=false
+CSET exclude_from_data_storage_13=false
+CSET exclude_from_data_storage_14=false
+CSET exclude_from_data_storage_15=false
+CSET exclude_from_data_storage_16=false
+CSET exclude_from_data_storage_2=false
+CSET exclude_from_data_storage_3=false
+CSET exclude_from_data_storage_4=false
+CSET exclude_from_data_storage_5=false
+CSET exclude_from_data_storage_6=false
+CSET exclude_from_data_storage_7=false
+CSET exclude_from_data_storage_8=false
+CSET exclude_from_data_storage_9=false
+CSET match_type_1=basic
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=4
+CSET sample_data_depth=512
+CSET sample_on=Rising
+CSET trigger_port_width_1=8
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=4
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE
+# CRC: 66151c7c
diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v
new file mode 100644
index 000000000..4c009d980
--- /dev/null
+++ b/fpga/usrp2/extramfifo/nobl_fifo.v
@@ -0,0 +1,96 @@
+// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port
+// device it can only sustain data throughput at half the RAM clock rate.
+// Fair arbitration to ensure this occurs is included in this logic and
+// requests for transactions that can not be completed are held off.
+// This FIFO requires a an external signal driving read_strobe that assures space for at least 6
+// reads since this the theopretical maximum number in flight due to pipeling.
+
+module nobl_fifo
+ #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+ (
+ input clk,
+ input rst,
+ input [WIDTH-1:0] RAM_D_pi,
+ output [WIDTH-1:0] RAM_D_po,
+ output RAM_D_poe,
+ output [RAM_DEPTH-1:0] RAM_A,
+ output RAM_WEn,
+ output RAM_CENn,
+ output RAM_LDn,
+ output RAM_OEn,
+ output RAM_CE1n,
+ input [WIDTH-1:0] write_data,
+ input write_strobe,
+ output reg space_avail,
+ output [WIDTH-1:0] read_data,
+ input read_strobe, // Triggers a read, result in approximately 6 cycles.
+ output data_avail, // Qulaifys read data available this cycle on read_data.
+ output reg [FIFO_DEPTH-1:0] capacity
+ );
+
+ //reg [FIFO_DEPTH-1:0] capacity;
+ reg [FIFO_DEPTH-1:0] wr_pointer;
+ reg [FIFO_DEPTH-1:0] rd_pointer;
+ wire [RAM_DEPTH-1:0] address;
+ reg data_avail_int; // Internal not empty flag.
+
+ assign read = read_strobe && data_avail_int;
+ assign write = write_strobe && space_avail;
+
+ // When a read and write collision occur, supress the space_avail flag next cycle
+ // and complete write followed by read over 2 cycles. This forces balanced arbitration
+ // and makes for a simple logic design.
+
+ always @(posedge clk)
+ if (rst)
+ begin
+ capacity <= (1 << FIFO_DEPTH) - 1;
+ wr_pointer <= 0;
+ rd_pointer <= 0;
+ space_avail <= 1;
+ data_avail_int <= 0;
+ end
+ else
+ begin
+ // No space available if:
+ // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision)
+ space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );
+ // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO.
+ data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) );
+ wr_pointer <= wr_pointer + write;
+ rd_pointer <= rd_pointer + (~write && read);
+ capacity <= capacity - write + (~write && read) ;
+ end // else: !if(rst)
+
+ assign address = write ? wr_pointer : rd_pointer;
+ assign enable = write || read;
+
+
+ //
+ // Simple NoBL SRAM interface, 4 cycle read latency.
+ // Read/Write arbitration via temprary application of empty/full flags.
+ //
+ nobl_if nobl_if_i1
+ (
+ .clk(clk),
+ .rst(rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .address(address),
+ .data_out(write_data),
+ .data_in(read_data),
+ .data_in_valid(data_avail),
+ .write(write),
+ .enable(enable)
+ );
+
+
+
+endmodule // nobl_fifo
diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v
new file mode 100644
index 000000000..391a841e8
--- /dev/null
+++ b/fpga/usrp2/extramfifo/nobl_if.v
@@ -0,0 +1,139 @@
+// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
+
+module nobl_if
+ #(parameter WIDTH=18,DEPTH=19)
+ (
+ input clk,
+ input rst,
+ input [WIDTH-1:0] RAM_D_pi,
+ output [WIDTH-1:0] RAM_D_po,
+ output reg RAM_D_poe,
+ output [DEPTH-1:0] RAM_A,
+ output reg RAM_WEn,
+ output RAM_CENn,
+ output RAM_LDn,
+ output RAM_OEn,
+ output reg RAM_CE1n,
+ input [DEPTH-1:0] address,
+ input [WIDTH-1:0] data_out,
+ output reg [WIDTH-1:0] data_in,
+ output reg data_in_valid,
+ input write,
+ input enable
+ );
+
+
+ reg enable_pipe1;
+ reg [DEPTH-1:0] address_pipe1;
+ reg write_pipe1;
+ reg [WIDTH-1:0] data_out_pipe1;
+
+ reg enable_pipe2;
+ reg write_pipe2;
+ reg [WIDTH-1:0] data_out_pipe2;
+
+ reg enable_pipe3;
+ reg write_pipe3;
+ reg [WIDTH-1:0] data_out_pipe3;
+
+ assign RAM_LDn = 0;
+ // ZBT/NoBL RAM actually manages its own output enables very well.
+ assign RAM_OEn = 0;
+
+ //
+ // Pipeline stage 1
+ //
+ always @(posedge clk)
+ if (rst)
+ begin
+ enable_pipe1 <= 0;
+ address_pipe1 <= 0;
+ write_pipe1 <= 0;
+ data_out_pipe1 <= 0;
+ end
+ else
+ begin
+ enable_pipe1 <= enable;
+ RAM_CE1n <= ~enable; // Creates IOB flob
+
+
+ if (enable)
+ begin
+ address_pipe1 <= address;
+ write_pipe1 <= write;
+ RAM_WEn <= ~write; // Creates IOB flob
+
+
+ if (write)
+ data_out_pipe1 <= data_out;
+ end
+ end // always @ (posedge clk)
+
+ // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
+ assign RAM_A = address_pipe1;
+ assign RAM_CENn = 1'b0;
+ // assign RAM_WEn = ~write_pipe1;
+// assign RAM_CE1n = ~enable_pipe1;
+
+ //
+ // Pipeline stage2
+ //
+ always @(posedge clk)
+ if (rst)
+ begin
+ enable_pipe2 <= 0;
+ data_out_pipe2 <= 0;
+ write_pipe2 <= 0;
+ end
+ else
+ begin
+ data_out_pipe2 <= data_out_pipe1;
+ write_pipe2 <= write_pipe1;
+ enable_pipe2 <= enable_pipe1;
+ end
+
+ //
+ // Pipeline stage3
+ //
+ always @(posedge clk)
+ if (rst)
+ begin
+ enable_pipe3 <= 0;
+ data_out_pipe3 <= 0;
+ write_pipe3 <= 0;
+ RAM_D_poe <= 0;
+ end
+ else
+ begin
+ data_out_pipe3 <= data_out_pipe2;
+ write_pipe3 <= write_pipe2;
+ enable_pipe3 <= enable_pipe2;
+ RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx.
+ end
+
+ // Pipeline 3 drives write data on NoBL SRAM
+ assign RAM_D_po = data_out_pipe3;
+
+
+ //
+ // Pipeline stage4
+ //
+ always @(posedge clk)
+ if (rst)
+ begin
+ data_in_valid <= 0;
+ data_in <= 0;
+ end
+ else
+ begin
+ data_in <= RAM_D_pi;
+ if (enable_pipe3 & ~write_pipe3)
+ begin
+ // Read data now available to be registered.
+ data_in_valid <= 1'b1;
+ end
+ else
+ data_in_valid <= 1'b0;
+ end // always @ (posedge clk)
+
+endmodule // nobl_if
diff --git a/fpga/usrp2/extramfifo/test_sram_if.v b/fpga/usrp2/extramfifo/test_sram_if.v
new file mode 100644
index 000000000..0e74b49eb
--- /dev/null
+++ b/fpga/usrp2/extramfifo/test_sram_if.v
@@ -0,0 +1,175 @@
+// Instantiate this block at the core level to conduct closed
+// loop testing of the AC performance of the USRP2 SRAM interface
+
+
+`define WIDTH 18
+`define DEPTH 19
+
+module test_sram_if
+ (
+ input clk,
+ input rst,
+ input [`WIDTH-1:0] RAM_D_pi,
+ output [`WIDTH-1:0] RAM_D_po,
+ output RAM_D_poe,
+ output [`DEPTH-1:0] RAM_A,
+ output RAM_WEn,
+ output RAM_CENn,
+ output RAM_LDn,
+ output RAM_OEn,
+ output RAM_CE1n,
+ output reg correct
+ );
+
+ reg [`DEPTH-1:0] write_count;
+ reg [`DEPTH-1:0] read_count;
+ reg enable;
+ reg write;
+ reg write_cycle;
+ reg read_cycle;
+ reg enable_reads;
+ reg [18:0] address;
+ reg [17:0] data_out;
+ wire [17:0] data_in;
+ wire data_in_valid;
+
+ reg [17:0] check_data;
+ reg [17:0] check_data_old;
+ reg [17:0] check_data_old2;
+
+ //
+ // Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM.
+ //
+
+ always @(posedge clk)
+ if (rst)
+ begin
+ write_count <= 19'h0;
+ read_count <= 19'h0;
+ end
+ else if (write_cycle) // Write cycle
+ if (write_count == 19'h7FFFF)
+ begin
+ write_count <= 19'h0;
+ end
+ else
+ begin
+ write_count <= write_count + 1'b1;
+ end
+ else if (read_cycle) // Read cycle
+ if (read_count == 19'h7FFFF)
+ begin
+ read_count <= 19'h0;
+ end
+ else
+ begin
+ read_count <= read_count + 1'b1;
+ end
+
+ always @(posedge clk)
+ if (rst)
+ begin
+ enable_reads <= 0;
+ read_cycle <= 0;
+ write_cycle <= 0;
+ end
+ else
+ begin
+ write_cycle <= ~write_cycle;
+ if (enable_reads)
+ read_cycle <= write_cycle;
+ if (write_count == 15) // Enable reads 15 writes after reset terminates.
+ enable_reads <= 1;
+ end // else: !if(rst)
+
+ always @(posedge clk)
+ if (rst)
+ begin
+ enable <= 0;
+ end
+ else if (write_cycle)
+ begin
+ address <= write_count;
+ data_out <= write_count[17:0];
+ enable <= 1;
+ write <= 1;
+ end
+ else if (read_cycle)
+ begin
+ address <= read_count;
+ check_data <= read_count[17:0];
+ check_data_old <= check_data;
+ check_data_old2 <= check_data_old;
+ enable <= 1;
+ write <= 0;
+ end
+ else
+ enable <= 0;
+
+ always @(posedge clk)
+ if (data_in_valid)
+ begin
+ correct <= (data_in == check_data_old2);
+ end
+
+
+ nobl_if nobl_if_i1
+ (
+ .clk(clk),
+ .rst(rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .address(address),
+ .data_out(data_out),
+ .data_in(data_in),
+ .data_in_valid(data_in_valid),
+ .write(write),
+ .enable(enable)
+ );
+
+
+ wire [35:0] CONTROL0;
+ reg [7:0] data_in_reg, data_out_reg, address_reg;
+ reg data_in_valid_reg,write_reg,enable_reg,correct_reg;
+
+ always @(posedge clk)
+ begin
+ data_in_reg <= data_in[7:0];
+ data_out_reg <= data_out[7:0];
+ data_in_valid_reg <= data_in_valid;
+ write_reg <= write;
+ enable_reg <= enable;
+ correct_reg <= correct;
+ address_reg <= address;
+
+ end
+
+
+ icon icon_i1
+ (
+ .CONTROL0(CONTROL0)
+ );
+
+ ila ila_i1
+ (
+ .CLK(clk),
+ .CONTROL(CONTROL0),
+ // .TRIG0(address_reg),
+ .TRIG0(data_in_reg[7:0]),
+ .TRIG1(data_out_reg[7:0]),
+ .TRIG2(address_reg[7:0]),
+ .TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg})
+ );
+
+
+
+endmodule // test_sram_if
+
+ \ No newline at end of file
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