Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 165 insertions, 0 deletions

diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v
new file mode 100644
index 000000000..0a64d3857
--- /dev/null
+++ b/fpga/usrp2/extramfifo/nobl_if.v
@@ -0,0 +1,165 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
+
+module nobl_if
+  #(parameter WIDTH=18,DEPTH=19)  
+    (
+     input clk,
+     input rst,
+     input [WIDTH-1:0] RAM_D_pi,
+     output [WIDTH-1:0] RAM_D_po,
+     output reg RAM_D_poe,
+     output [DEPTH-1:0] RAM_A,
+     output reg RAM_WEn,
+     output RAM_CENn,
+     output RAM_LDn,
+     output RAM_OEn,
+     output reg RAM_CE1n,
+     input [DEPTH-1:0] address,
+     input [WIDTH-1:0] data_out,
+     output reg [WIDTH-1:0] data_in,
+     output reg data_in_valid,
+     input write,
+     input enable
+     );
+   
+
+   reg 	   enable_pipe1;
+   reg [DEPTH-1:0] address_pipe1;
+   reg 		   write_pipe1;
+   reg [WIDTH-1:0] data_out_pipe1;
+   
+   reg 		   enable_pipe2;
+   reg 		   write_pipe2;
+   reg [WIDTH-1:0] data_out_pipe2;
+
+   reg 		   enable_pipe3;
+   reg 		   write_pipe3;
+   reg [WIDTH-1:0] data_out_pipe3;
+
+   assign 	   RAM_LDn = 0;
+   // ZBT/NoBL RAM actually manages its own output enables very well.
+   assign 	   RAM_OEn = 0;
+
+   // gray code the address to reduce EMI
+   wire [DEPTH-1:0] address_gray;
+   
+   bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray));
+   
+   
+   //
+   // Pipeline stage 1
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe1 <= 0;
+	  address_pipe1 <= 0;
+	  write_pipe1 <= 0;
+	  data_out_pipe1  <= 0;
+	  RAM_WEn <= 1;
+	  RAM_CE1n <= 1;
+	  
+       end
+     else
+       begin
+	  enable_pipe1 <= enable;
+	  RAM_CE1n <= ~enable;  // Creates IOB flop
+	  RAM_WEn <= ~write;  // Creates IOB flop
+	  
+	  if (enable)
+	    begin
+	       address_pipe1 <= address_gray;
+	       write_pipe1 <= write;
+//	       RAM_WEn <= ~write;  // Creates IOB flop
+	       
+	       
+	       if (write)
+		 data_out_pipe1 <= data_out;
+	    end
+       end // always @ (posedge clk)
+
+   // Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
+   assign RAM_A = address_pipe1;
+   assign RAM_CENn = 1'b0;
+ //  assign RAM_WEn = ~write_pipe1;
+//   assign RAM_CE1n = ~enable_pipe1;
+
+   //
+   // Pipeline stage2
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe2 <= 0;
+	  data_out_pipe2 <= 0;
+	  write_pipe2 <= 0;   
+       end
+     else
+       begin
+	  data_out_pipe2 <= data_out_pipe1;
+	  write_pipe2 <= write_pipe1;
+	  enable_pipe2 <= enable_pipe1;
+       end
+   
+   //
+   // Pipeline stage3
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  enable_pipe3 <= 0;
+	  data_out_pipe3 <= 0;
+	  write_pipe3 <= 0;
+	  RAM_D_poe <= 0;	  
+       end
+     else
+       begin
+	  data_out_pipe3 <= data_out_pipe2;
+	  write_pipe3 <= write_pipe2;
+	  enable_pipe3 <= enable_pipe2;
+	  RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx.	
+       end
+
+   // Pipeline 3 drives write data on NoBL SRAM
+   assign RAM_D_po = data_out_pipe3;
+   
+   
+   //
+   // Pipeline stage4
+   //
+   always @(posedge clk)
+     if (rst)
+       begin
+	  data_in_valid <= 0;
+	  data_in <= 0;
+       end
+     else
+       begin
+	  data_in <= RAM_D_pi;
+	  if (enable_pipe3 & ~write_pipe3)
+	    begin
+	       // Read data now available to be registered.
+	       data_in_valid <= 1'b1;
+	    end
+	  else
+	    data_in_valid <= 1'b0;
+       end // always @ (posedge clk)
+     
+endmodule // nobl_if