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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:53:14 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:53:14 -0800 |
| commit | 18ce33d2286a428705bc19e5dc091f2d6a6d4d5b (patch) | |
| tree | c355fbde9d8804b29ab76bef7412874fe03955a1 /fpga/usrp2/extramfifo/nobl_fifo.v | |
| parent | 30ce5acedd3e0dc6fc97d7597781a0a4828812f2 (diff) | |
| parent | 74bb6b39d9a677e6a7a41b6e3d62488aa265f706 (diff) | |
| download | uhd-18ce33d2286a428705bc19e5dc091f2d6a6d4d5b.tar.gz uhd-18ce33d2286a428705bc19e5dc091f2d6a6d4d5b.tar.bz2 uhd-18ce33d2286a428705bc19e5dc091f2d6a6d4d5b.zip | |
Merge branch 'fpga_next' into next
Conflicts:
fpga/usrp2/top/u1e_passthru/.gitignore
fpga/usrp2/top/u1e_passthru/Makefile
fpga/usrp2/top/u2plus/.gitignore
fpga/usrp2/top/u2plus/Makefile
usrp2/top/u1e_passthru/.gitignore
usrp2/top/u1e_passthru/Makefile
Diffstat (limited to 'fpga/usrp2/extramfifo/nobl_fifo.v')
| -rw-r--r-- | fpga/usrp2/extramfifo/nobl_fifo.v | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v index 4c009d980..0b63768fc 100644 --- a/fpga/usrp2/extramfifo/nobl_fifo.v +++ b/fpga/usrp2/extramfifo/nobl_fifo.v @@ -70,26 +70,27 @@ module nobl_fifo // Simple NoBL SRAM interface, 4 cycle read latency. // Read/Write arbitration via temprary application of empty/full flags. // - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); + nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) + nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); |