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| author | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-14 16:55:56 -0700 |
| commit | 26b7de0ac0cd64946582b2d52ab0bb3555156039 (patch) | |
| tree | 5dc670eaaab60bf2bda90d905210bc9432cecea3 /fpga/usrp2/extramfifo/icon.xco | |
| parent | 71e1763332141603e9edba097fd19b00e9a76ab8 (diff) | |
| parent | ee03f1d4acf5c7d3359c86baba5085660d63ebae (diff) | |
| download | uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.gz uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.tar.bz2 uhd-26b7de0ac0cd64946582b2d52ab0bb3555156039.zip | |
Merge branch 'flow_control' into flow_ctrl
Diffstat (limited to 'fpga/usrp2/extramfifo/icon.xco')
| -rw-r--r-- | fpga/usrp2/extramfifo/icon.xco | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/icon.xco b/fpga/usrp2/extramfifo/icon.xco new file mode 100644 index 000000000..fda273149 --- /dev/null +++ b/fpga/usrp2/extramfifo/icon.xco @@ -0,0 +1,47 @@ +############################################################## +# +# Xilinx Core Generator version 12.1 +# Date: Wed Jul 21 03:31:19 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET enable_jtag_bufg=true +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE +# CRC: 799ba5a1 |