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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
| commit | f56c1247cbe7b7e90acee2711b5dda3356b9486a (patch) | |
| tree | 81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/extramfifo/fifo_extram36_tb.build | |
| parent | 9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff) | |
| parent | eb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff) | |
| download | uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.gz uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.bz2 uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.zip | |
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram36_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram36_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100755 index 000000000..ac9369758 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v |