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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
| commit | d35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch) | |
| tree | 0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/extramfifo/ext_fifo_tb.cmd | |
| parent | 6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff) | |
| parent | 768af46dc01d036999cb60ff16df4215d014c906 (diff) | |
| download | uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.gz uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.bz2 uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.zip | |
Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/extramfifo/ext_fifo_tb.cmd')
| -rw-r--r-- | fpga/usrp2/extramfifo/ext_fifo_tb.cmd | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd new file mode 100644 index 000000000..521f88f21 --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd @@ -0,0 +1,12 @@ +/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v +-y . +-y ../coregen/ +-y ../fifo +-y ../models +-y /home/ianb/usrp-fpga/usrp2/sdr_lib +-y /home/ianb/usrp-fpga/usrp2/control_lib +-y /home/ianb/usrp-fpga/usrp2/models +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib + |