Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

6 files changed, 453 insertions, 0 deletions

diff --git a/fpga/usrp2/custom/custom_dsp_rx.v b/fpga/usrp2/custom/custom_dsp_rx.v
new file mode 100644
index 000000000..355adf008
--- /dev/null
+++ b/fpga/usrp2/custom/custom_dsp_rx.v
@@ -0,0 +1,71 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//COPY ME, CUSTOMIZE ME...
+
+//The following module effects the IO of the DDC chain.
+//By default, this entire module is a simple pass-through.
+
+//To implement DSP logic before the DDC:
+//Implement custom DSP between frontend and ddc input.
+
+//To implement DSP logic after the DDC:
+//Implement custom DSP between ddc output and baseband.
+
+//To bypass the DDC with custom logic:
+//Implement custom DSP between frontend and baseband.
+
+module custom_dsp_rx
+#(
+    //frontend bus width
+    parameter WIDTH = 24
+)
+(
+    //control signals
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //full rate inputs directly from the RX frontend
+    input [WIDTH-1:0] frontend_i,
+    input [WIDTH-1:0] frontend_q,
+
+    //full rate outputs directly to the DDC chain
+    output [WIDTH-1:0] ddc_in_i,
+    output [WIDTH-1:0] ddc_in_q,
+
+    //strobed samples {I16,Q16} from the RX DDC chain
+    input [31:0] ddc_out_sample,
+    input ddc_out_strobe, //high on valid sample
+    output ddc_out_enable, //enables DDC module
+
+    //strobbed baseband samples {I16,Q16} from this module
+    output [31:0] bb_sample,
+    output bb_strobe //high on valid sample
+);
+
+    assign ddc_in_i = frontend_i;
+    assign ddc_in_q = frontend_q;
+    assign bb_sample = ddc_out_sample;
+    assign bb_strobe = ddc_out_strobe;
+    assign ddc_out_enable = enable;
+
+endmodule //custom_dsp_rx
diff --git a/fpga/usrp2/custom/custom_dsp_tx.v b/fpga/usrp2/custom/custom_dsp_tx.v
new file mode 100644
index 000000000..0848a187f
--- /dev/null
+++ b/fpga/usrp2/custom/custom_dsp_tx.v
@@ -0,0 +1,71 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//COPY ME, CUSTOMIZE ME...
+
+//The following module effects the IO of the DUC chain.
+//By default, this entire module is a simple pass-through.
+
+//To implement DSP logic before the DUC:
+//Implement custom DSP between baseband and duc input.
+
+//To implement DSP logic after the DUC:
+//Implement custom DSP between duc output and frontend.
+
+//To bypass the DUC with custom logic:
+//Implement custom DSP between baseband and frontend.
+
+module custom_dsp_tx
+#(
+    //frontend bus width
+    parameter WIDTH = 24
+)
+(
+    //control signals
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //full rate outputs directly to the TX frontend
+    output [WIDTH-1:0] frontend_i,
+    output [WIDTH-1:0] frontend_q,
+
+    //full rate outputs directly from the DUC chain
+    input [WIDTH-1:0] duc_out_i,
+    input [WIDTH-1:0] duc_out_q,
+
+    //strobed samples {I16,Q16} to the TX DUC chain
+    output [31:0] duc_in_sample,
+    input duc_in_strobe, //this is a backpressure signal
+    output duc_in_enable, //enables DUC module
+
+    //strobbed baseband samples {I16,Q16} to this module
+    input [31:0] bb_sample,
+    output bb_strobe //this is a backpressure signal
+);
+
+    assign frontend_i = duc_out_i;
+    assign frontend_q = duc_out_q;
+    assign duc_in_sample = bb_sample;
+    assign bb_strobe = duc_in_strobe;
+    assign duc_in_enable = enable;
+
+endmodule //custom_dsp_tx
diff --git a/fpga/usrp2/custom/custom_engine_rx.v b/fpga/usrp2/custom/custom_engine_rx.v
new file mode 100644
index 000000000..dfeaad2cd
--- /dev/null
+++ b/fpga/usrp2/custom/custom_engine_rx.v
@@ -0,0 +1,53 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//COPY ME, CUSTOMIZE ME...
+
+//The following module is used to re-write receive packets to the host.
+//This module provides a packet-based ram interface for manipulating packets.
+//The user writes a custom engine (state machine) to read the input packet,
+//and to produce a new output packet.
+
+//By default, this entire module is a simple pass-through.
+
+module custom_engine_rx
+#(
+    //buffer size for ram interface engine
+    parameter BUF_SIZE = 10
+)
+(
+    //control signals
+    input clock, input reset, input clear,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //ram interface for engine
+    output access_we,
+    output access_stb,
+    input access_ok,
+    output access_done,
+    output access_skip_read,
+    output [BUF_SIZE-1:0] access_adr,
+    input [BUF_SIZE-1:0] access_len,
+    output [35:0] access_dat_o,
+    input [35:0] access_dat_i
+);
+
+    assign access_done = access_ok;
+
+endmodule //custom_engine_rx
diff --git a/fpga/usrp2/custom/custom_engine_tx.v b/fpga/usrp2/custom/custom_engine_tx.v
new file mode 100644
index 000000000..9be728484
--- /dev/null
+++ b/fpga/usrp2/custom/custom_engine_tx.v
@@ -0,0 +1,57 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+//COPY ME, CUSTOMIZE ME...
+
+//The following module is used to re-write transmit packets from the host.
+//This module provides a packet-based ram interface for manipulating packets.
+//The user writes a custom engine (state machine) to read the input packet,
+//and to produce a new output packet.
+
+//By default, this entire module is a simple pass-through.
+
+module custom_engine_tx
+#(
+    //buffer size for ram interface engine
+    parameter BUF_SIZE = 10,
+
+    //the number of 32bit lines between start of buffer and vita header
+    //the metadata before the header should be preserved by the engine
+    parameter HEADER_OFFSET = 0
+)
+(
+    //control signals
+    input clock, input reset, input clear,
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //ram interface for engine
+    output access_we,
+    output access_stb,
+    input access_ok,
+    output access_done,
+    output access_skip_read,
+    output [BUF_SIZE-1:0] access_adr,
+    input [BUF_SIZE-1:0] access_len,
+    output [35:0] access_dat_o,
+    input [35:0] access_dat_i
+);
+
+    assign access_done = access_ok;
+
+endmodule //custom_engine_tx
diff --git a/fpga/usrp2/custom/power_trig.v b/fpga/usrp2/custom/power_trig.v
new file mode 100644
index 000000000..b38059030
--- /dev/null
+++ b/fpga/usrp2/custom/power_trig.v
@@ -0,0 +1,130 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// This a power trigger module implemented on top of the custom dsp template.
+// Power triggering is implemented after the existing DDC chain.
+// Triggering is controlled via user settings registers.
+
+// Register 0:
+//  threshold for power trigger
+//  32 bit unsigned fixed-point number of some arbitrary scaling
+
+module power_trig
+#(
+    //frontend bus width
+    parameter WIDTH = 24,
+    parameter BASE = 0
+)
+(
+    //control signals
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
+
+    //user settings bus, controlled through user setting regs API
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //full rate inputs directly from the RX frontend
+    input [WIDTH-1:0] frontend_i,
+    input [WIDTH-1:0] frontend_q,
+
+    //full rate outputs directly to the DDC chain
+    output [WIDTH-1:0] ddc_in_i,
+    output [WIDTH-1:0] ddc_in_q,
+
+    //strobed samples {I16,Q16} from the RX DDC chain
+    input [31:0] ddc_out_sample,
+    input ddc_out_strobe, //high on valid sample
+    output ddc_out_enable, //enables DDC module
+
+    //strobbed baseband samples {I16,Q16} from this module
+    output [31:0] bb_sample,
+    output bb_strobe //high on valid sample
+);
+
+    //leave frontend tied to existing ddc chain
+    assign ddc_in_i = frontend_i;
+    assign ddc_in_q = frontend_q;
+
+    //ddc enable remains tied to global enable
+    assign ddc_out_enable = enable;
+
+    //below we implement a power trigger between baseband samples and ddc output...
+
+   reg [8:0] 	  wr_addr;
+   wire [8:0] 	  rd_addr;
+   reg 		  triggered, triggerable;
+   wire 	  trigger;
+   
+   wire [31:0] 	  delayed_sample;
+   wire [31:0] 	  thresh;
+   
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(thresh),.changed());
+
+   assign rd_addr = wr_addr + 1; // FIXME adjustable delay
+
+   ram_2port  #(.DWIDTH(32),.AWIDTH(9)) delay_line
+     (.clka(clk),.ena(1),.wea(ddc_out_strobe),.addra(wr_addr),.dia(ddc_out_sample),.doa(),
+      .clkb(clk),.enb(ddc_out_strobe),.web(1'b0),.addrb(rd_addr),.dib(32'hFFFF),.dob(delayed_sample));
+
+   always @(posedge clock)
+     if(reset | ~enable)
+       wr_addr <= 0;
+     else
+       if(ddc_out_strobe)
+	 wr_addr <= wr_addr + 1;
+
+   always @(posedge clock)
+     if(reset | ~enable)
+       triggerable <= 0;
+     else if(wr_addr == 9'h1FF)  // Wait till we're nearly full
+       triggerable <= 1;
+   
+
+   reg 			      stb_d1, stb_d2;
+   always @(posedge clock) stb_d1 <= ddc_out_strobe;
+   always @(posedge clock) stb_d2 <= stb_d1;
+   
+   assign bb_sample = delayed_sample;
+   assign bb_strobe = stb_d1 & triggered;
+
+   // Compute Mag
+   wire [17:0] 		      mult_in = stb_d1 ? { ddc_out_sample[15],ddc_out_sample[15:0], 1'b0 } : 
+			      { ddc_out_sample[31], ddc_out_sample[31:16], 1'b0 };
+   wire [35:0] 		      prod;
+   reg [31:0] 		      sum;
+   
+   MULT18X18S mult (.P(prod), .A(mult_in), .B(mult_in), .C(clock), .CE(ddc_out_strobe | stb_d1), .R(reset) );
+
+   always @(posedge clock)
+     if(stb_d1)
+       sum <= prod[35:4];
+     else if(stb_d2)
+       sum <= sum + prod[35:4];
+
+   always @(posedge clock)
+     if(reset | ~enable | ~triggerable)
+       triggered <= 0;
+     else if(trigger)
+       triggered <= 1;
+
+   assign trigger = (sum > thresh);
+   
+endmodule // power_trig
diff --git a/fpga/usrp2/custom/power_trig_tb.v b/fpga/usrp2/custom/power_trig_tb.v
new file mode 100644
index 000000000..b8f3385ce
--- /dev/null
+++ b/fpga/usrp2/custom/power_trig_tb.v
@@ -0,0 +1,71 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module power_trig_tb();
+   initial $dumpfile("power_trig_tb.vcd");
+   initial $dumpvars(0,power_trig_tb);
+
+   reg clk = 0;
+   always #10 clk <= ~clk;
+   reg rst = 1;
+   initial #100 rst <= 0;
+
+   initial
+     begin
+	set_stb <= 0;
+	#1000;
+	set_stb <= 1;
+     end
+   
+   reg [31:0] sample_in;
+   reg 	      strobe_in;
+   wire [31:0] sample_out;
+   wire        strobe_out;
+   reg 	       set_stb, run;
+   
+   power_trig #(.BASE(0)) power_trig
+     (.clk(clk), .reset(rst), .enable(1),
+      .set_stb(set_stb), .set_addr(0), .set_data(32'h000B_B000),
+      .run(run),
+
+      .ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in),
+      .bb_sample(sample_out), .bb_strobe(strobe_out));
+
+   initial sample_in <= 32'h0100_0300;
+   
+   always @(posedge clk)
+     if(~strobe_in)
+       sample_in <= sample_in + 32'h0001_0001;
+
+   initial
+     #100000 $finish;
+
+   initial 
+     begin
+	run <= 0;
+	#2000 run <= 1;
+	#30000 run <= 0;
+     end
+
+   always @(posedge clk)
+     if(rst | ~run)
+       strobe_in <= 0;
+     else
+       strobe_in <= ~strobe_in;
+   
+endmodule // power_trig_tb