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authorJosh Blum <josh@joshknows.com>2010-11-23 15:35:48 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 15:35:48 -0800
commitf56c1247cbe7b7e90acee2711b5dda3356b9486a (patch)
tree81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/coregen
parent9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff)
parenteb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff)
downloaduhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.gz
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Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Diffstat (limited to 'fpga/usrp2/coregen')
-rw-r--r--fpga/usrp2/coregen/Makefile.srcs8
-rw-r--r--fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs15
-rw-r--r--fpga/usrp2/coregen/coregen.cgp24
-rw-r--r--fpga/usrp2/coregen/fifo_generator_ug175.pdfbin1069823 -> 2895895 bytes
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf0
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v3839
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt12
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt46
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf0
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v173
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo53
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt12
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf0
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v169
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo51
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt12
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl68
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise30
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v173
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo53
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco84
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise72
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt12
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl68
43 files changed, 5857 insertions, 11 deletions
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs
index 7b29225ca..a3a5d826d 100644
--- a/fpga/usrp2/coregen/Makefile.srcs
+++ b/fpga/usrp2/coregen/Makefile.srcs
@@ -16,4 +16,12 @@ fifo_xlnx_16x19_2clk.v \
fifo_xlnx_16x19_2clk.xco \
fifo_xlnx_16x40_2clk.v \
fifo_xlnx_16x40_2clk.xco \
+fifo_xlnx_32x36_2clk.v \
+fifo_xlnx_32x36_2clk.xco \
+fifo_xlnx_512x36_2clk_36to18.v \
+fifo_xlnx_512x36_2clk_36to18.xco \
+fifo_xlnx_512x36_2clk_18to36.v \
+fifo_xlnx_512x36_2clk_18to36.xco \
+fifo_xlnx_512x36_2clk_prog_full.v \
+fifo_xlnx_512x36_2clk_prog_full.xco \
))
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 000000000..d946af064
--- /dev/null
+++ b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/uhdpriv/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp
index 810d64dac..dd85a7f50 100644
--- a/fpga/usrp2/coregen/coregen.cgp
+++ b/fpga/usrp2/coregen/coregen.cgp
@@ -1,20 +1,22 @@
-# Date: Thu Sep 3 17:40:48 2009
-SET addpads = False
-SET asysymbol = False
+# Date: Fri Oct 15 07:50:19 2010
+
+SET addpads = false
+SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
+SET createndf = false
SET designentry = Verilog
SET device = xc3s2000
SET devicefamily = spartan3
SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
+SET formalverification = false
+SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg456
-SET removerpms = False
-SET simulationfiles = Behavioral
+SET removerpms = false
+SET simulationfiles = Structural
SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-SET workingdirectory = /home/matt/coregen/tmp
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = /tmp/
+# CRC: 983b9b45
diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
index 2c3e3c200..5fba6029c 100644
--- a/fpga/usrp2/coregen/fifo_generator_ug175.pdf
+++ b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
Binary files differ
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
new file mode 100644
index 000000000..70ee54054
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_32x36_2clk.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_32x36_2clk.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
new file mode 100644
index 000000000..d1ed419a7
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
new file mode 100644
index 000000000..68a8caaf6
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
@@ -0,0 +1,3839 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.63c
+// \ \ Application: netgen
+// / / Filename: fifo_xlnx_32x36_2clk.v
+// /___/ /\ Timestamp: Fri Oct 15 00:50:08 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v
+// Device : 3s2000fg456-5
+// Input file : /tmp/_cg/fifo_xlnx_32x36_2clk.ngc
+// Output file : /tmp/_cg/fifo_xlnx_32x36_2clk.v
+// # of Modules : 1
+// Design Name : fifo_xlnx_32x36_2clk
+// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module fifo_xlnx_32x36_2clk (
+ rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input rd_en;
+ output almost_full;
+ output prog_full;
+ input wr_en;
+ output full;
+ output empty;
+ input wr_clk;
+ input rst;
+ input rd_clk;
+ output [35 : 0] dout;
+ input [35 : 0] din;
+
+ // synthesis translate_off
+
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ;
+ wire \BU2/N16 ;
+ wire \BU2/N14 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ;
+ wire \BU2/U0/grf.rf/mem/dout_i_not0001 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ;
+ wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
+ wire \BU2/N1 ;
+ wire NLW_VCC_P_UNCONNECTED;
+ wire NLW_GND_G_UNCONNECTED;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ;
+ wire [35 : 0] din_2;
+ wire [35 : 0] dout_3;
+ wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ;
+ wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
+ wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ;
+ wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ;
+ wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ;
+ wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ;
+ wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
+ wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
+ wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
+ wire [0 : 0] \BU2/rd_data_count ;
+ assign
+ dout[35] = dout_3[35],
+ dout[34] = dout_3[34],
+ dout[33] = dout_3[33],
+ dout[32] = dout_3[32],
+ dout[31] = dout_3[31],
+ dout[30] = dout_3[30],
+ dout[29] = dout_3[29],
+ dout[28] = dout_3[28],
+ dout[27] = dout_3[27],
+ dout[26] = dout_3[26],
+ dout[25] = dout_3[25],
+ dout[24] = dout_3[24],
+ dout[23] = dout_3[23],
+ dout[22] = dout_3[22],
+ dout[21] = dout_3[21],
+ dout[20] = dout_3[20],
+ dout[19] = dout_3[19],
+ dout[18] = dout_3[18],
+ dout[17] = dout_3[17],
+ dout[16] = dout_3[16],
+ dout[15] = dout_3[15],
+ dout[14] = dout_3[14],
+ dout[13] = dout_3[13],
+ dout[12] = dout_3[12],
+ dout[11] = dout_3[11],
+ dout[10] = dout_3[10],
+ dout[9] = dout_3[9],
+ dout[8] = dout_3[8],
+ dout[7] = dout_3[7],
+ dout[6] = dout_3[6],
+ dout[5] = dout_3[5],
+ dout[4] = dout_3[4],
+ dout[3] = dout_3[3],
+ dout[2] = dout_3[2],
+ dout[1] = dout_3[1],
+ dout[0] = dout_3[0],
+ din_2[35] = din[35],
+ din_2[34] = din[34],
+ din_2[33] = din[33],
+ din_2[32] = din[32],
+ din_2[31] = din[31],
+ din_2[30] = din[30],
+ din_2[29] = din[29],
+ din_2[28] = din[28],
+ din_2[27] = din[27],
+ din_2[26] = din[26],
+ din_2[25] = din[25],
+ din_2[24] = din[24],
+ din_2[23] = din[23],
+ din_2[22] = din[22],
+ din_2[21] = din[21],
+ din_2[20] = din[20],
+ din_2[19] = din[19],
+ din_2[18] = din[18],
+ din_2[17] = din[17],
+ din_2[16] = din[16],
+ din_2[15] = din[15],
+ din_2[14] = din[14],
+ din_2[13] = din[13],
+ din_2[12] = din[12],
+ din_2[11] = din[11],
+ din_2[10] = din[10],
+ din_2[9] = din[9],
+ din_2[8] = din[8],
+ din_2[7] = din[7],
+ din_2[6] = din[6],
+ din_2[5] = din[5],
+ din_2[4] = din[4],
+ din_2[3] = din[3],
+ din_2[2] = din[2],
+ din_2[1] = din[1],
+ din_2[0] = din[0];
+ VCC VCC_0 (
+ .P(NLW_VCC_P_UNCONNECTED)
+ );
+ GND GND_1 (
+ .G(NLW_GND_G_UNCONNECTED)
+ );
+ LUT3_L #(
+ .INIT ( 8'h90 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ),
+ .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h8241 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 )
+ );
+ LUT3_L #(
+ .INIT ( 8'h7F ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 )
+ );
+ LUT3_L #(
+ .INIT ( 8'h7F ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 )
+ );
+ LUT2_L #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .LO(\BU2/N16 )
+ );
+ LUT2_L #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .LO(\BU2/N14 )
+ );
+ INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 (
+ .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
+ );
+ INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 (
+ .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 )
+ );
+ LUT4 #(
+ .INIT ( 16'h2333 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6AAA ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6AAA ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
+ );
+ LUT3 #(
+ .INIT ( 8'h08 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 )
+ );
+ LUT3 #(
+ .INIT ( 8'h10 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I2(wr_en),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 )
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 )
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h5450 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 (
+ .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 )
+ );
+ LUT4 #(
+ .INIT ( 16'h5450 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 (
+ .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 )
+ );
+ LUT4 #(
+ .INIT ( 16'hECA0 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8241 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 )
+ );
+ LUT4 #(
+ .INIT ( 16'h2333 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA6 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA6 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9])
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/N16 ),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/N14 ),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA2 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(rd_en),
+ .O(\BU2/U0/grf.rf/mem/dout_i_not0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'hD ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8E8A ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(rd_en),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
+ );
+ LUT4 #(
+ .INIT ( 16'h40FF ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0])
+ );
+ LUT3 #(
+ .INIT ( 8'h6A ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
+ );
+ LUT3 #(
+ .INIT ( 8'h6A ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
+ );
+ LUT3 #(
+ .INIT ( 8'h96 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'h96 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'hF2 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I1(rd_en),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1])
+ );
+ LUT3 #(
+ .INIT ( 8'h08 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]),
+ .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_comb1 (
+ .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ),
+ .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+ .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_comb1 (
+ .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ),
+ .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+ .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(almost_full)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(full)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]),
+ .Q(dout_3[0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]),
+ .Q(dout_3[1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]),
+ .Q(dout_3[2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]),
+ .Q(dout_3[3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]),
+ .Q(dout_3[4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_5 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]),
+ .Q(dout_3[5])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_6 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]),
+ .Q(dout_3[6])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_7 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]),
+ .Q(dout_3[7])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_8 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]),
+ .Q(dout_3[8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_9 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]),
+ .Q(dout_3[9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_10 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]),
+ .Q(dout_3[10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_11 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]),
+ .Q(dout_3[11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_12 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]),
+ .Q(dout_3[12])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_13 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]),
+ .Q(dout_3[13])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_14 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]),
+ .Q(dout_3[14])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_15 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]),
+ .Q(dout_3[15])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_16 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]),
+ .Q(dout_3[16])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_17 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]),
+ .Q(dout_3[17])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_18 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]),
+ .Q(dout_3[18])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_19 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]),
+ .Q(dout_3[19])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_20 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]),
+ .Q(dout_3[20])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_21 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]),
+ .Q(dout_3[21])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_22 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]),
+ .Q(dout_3[22])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_23 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]),
+ .Q(dout_3[23])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_24 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]),
+ .Q(dout_3[24])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_25 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]),
+ .Q(dout_3[25])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_26 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]),
+ .Q(dout_3[26])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_27 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]),
+ .Q(dout_3[27])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_28 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]),
+ .Q(dout_3[28])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_29 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]),
+ .Q(dout_3[29])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_30 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]),
+ .Q(dout_3[30])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_31 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]),
+ .Q(dout_3[31])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_32 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]),
+ .Q(dout_3[32])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_33 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]),
+ .Q(dout_3[33])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_34 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]),
+ .Q(dout_3[34])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_35 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]),
+ .Q(dout_3[35])
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[35]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[35]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[34]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[34]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[33]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[32]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[33]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[32]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[31]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[31]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[30]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[29]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[29]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[30]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[28]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[28]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[27]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[27]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[26]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[25]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[26]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[24]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[24]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[25]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[23]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[22]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[23]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[22]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[21]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[21]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[20]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[19]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[19]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[20]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[18]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[18]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[17]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[17]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[16]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[15]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[16]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[15]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[14]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[14]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[13]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[12]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[12]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[13]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[11]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[11]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[10]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[10]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[9]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[8]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[9]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[8]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[7]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[7]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[6]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[5]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[5]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[6]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[4]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[4]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[3]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[3]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[2]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[1]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[2]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[1]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[0]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[0]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(prog_full)
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> (
+ .CI(\BU2/N1 ),
+ .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .S(\BU2/rd_data_count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4])
+ );
+ XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+ .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4])
+ );
+ XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]),
+ .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(empty)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d1 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 )
+ );
+ FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 )
+ );
+ FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d2 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d3 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 )
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/RST_FULL_GEN (
+ .C(wr_clk),
+ .CLR(rst),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ),
+ .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 )
+ );
+ VCC \BU2/XST_VCC (
+ .P(\BU2/N1 )
+ );
+ GND \BU2/XST_GND (
+ .G(\BU2/rd_data_count [0])
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
new file mode 100644
index 000000000..eb98a2b70
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
@@ -0,0 +1,47 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_32x36_2clk YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [35 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [35 : 0]
+ .full(full),
+ .almost_full(almost_full),
+ .empty(empty),
+ .prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
new file mode 100644
index 000000000..1cf4c8ba5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Fri Oct 15 07:50:15 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_32x36_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=24
+CSET full_threshold_negate_value=23
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=32
+CSET output_data_width=36
+CSET output_depth=32
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 8e84ee7f
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
new file mode 100644
index 000000000..b9eb7bd1a
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_xlnx_32x36_2clk.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="fifo_xlnx_32x36_2clk.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_32x36_2clk.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-15T00:50:17" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8449944117490A53CFE9CD2127BE2AA" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
new file mode 100644
index 000000000..b8c69a9f7
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_32x36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_32x36_2clk.gise
+fifo_xlnx_32x36_2clk.ngc
+fifo_xlnx_32x36_2clk.v
+fifo_xlnx_32x36_2clk.veo
+fifo_xlnx_32x36_2clk.xco
+fifo_xlnx_32x36_2clk.xise
+fifo_xlnx_32x36_2clk_flist.txt
+fifo_xlnx_32x36_2clk_readme.txt
+fifo_xlnx_32x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
new file mode 100644
index 000000000..8ab5679fd
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
@@ -0,0 +1,46 @@
+The following files were generated for 'fifo_xlnx_32x36_2clk' in directory
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+ Please see the core data sheet.
+
+fifo_xlnx_32x36_2clk.gise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_32x36_2clk.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_32x36_2clk.v:
+ Unisim Verilog file containing the information required to simulate
+ the module.
+
+fifo_xlnx_32x36_2clk.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_32x36_2clk.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_32x36_2clk.xise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_32x36_2clk_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_32x36_2clk_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+fifo_xlnx_32x36_2clk_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..ec9426357
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_32x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_32x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk
+}
+# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise
new file mode 100644
index 000000000..c18cf3bf0
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_18to36.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
new file mode 100644
index 000000000..d9277b0c3
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
new file mode 100644
index 000000000..25ac9779e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating
+// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_18to36(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ almost_full,
+ empty,
+ prog_full);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [17 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output almost_full;
+output empty;
+output prog_full;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V6_1 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(10),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(18),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(36),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(0),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(1),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(0),
+ .C_PRELOAD_REGS(1),
+ .C_PRIM_FIFO_TYPE("1kx18"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(1015),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(1014),
+ .C_PROG_FULL_TYPE(1),
+ .C_RD_DATA_COUNT_WIDTH(9),
+ .C_RD_DEPTH(512),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(9),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(10),
+ .C_WR_DEPTH(1024),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(10),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .ALMOST_FULL(almost_full),
+ .EMPTY(empty),
+ .PROG_FULL(prog_full),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo
new file mode 100644
index 000000000..db2795098
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk_18to36 YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [17 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [35 : 0]
+ .full(full),
+ .almost_full(almost_full),
+ .empty(empty),
+ .prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_18to36.v when simulating
+// the core, fifo_xlnx_512x36_2clk_18to36. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
new file mode 100644
index 000000000..f888ba5f4
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Wed Aug 18 17:27:35 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_512x36_2clk_18to36
+CSET data_count=false
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=1015
+CSET full_threshold_negate_value=1014
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=18
+CSET input_depth=1024
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: 77234081
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise
new file mode 100644
index 000000000..04acaf578
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_18to36.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_18to36.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_18to36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-18T10:27:37" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="224FA43C81F32871F9E1930EA6CDD6AD" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt
new file mode 100644
index 000000000..2f8d522f6
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_512x36_2clk_18to36>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_512x36_2clk_18to36.gise
+fifo_xlnx_512x36_2clk_18to36.ngc
+fifo_xlnx_512x36_2clk_18to36.v
+fifo_xlnx_512x36_2clk_18to36.veo
+fifo_xlnx_512x36_2clk_18to36.xco
+fifo_xlnx_512x36_2clk_18to36.xise
+fifo_xlnx_512x36_2clk_18to36_flist.txt
+fifo_xlnx_512x36_2clk_18to36_readme.txt
+fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt
new file mode 100644
index 000000000..03829e876
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt
@@ -0,0 +1,47 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+ Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_18to36.gise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_18to36.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk_18to36.v:
+ Verilog wrapper file provided to support functional simulation.
+ This file contains simulation model customization data that is
+ passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk_18to36.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk_18to36.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_512x36_2clk_18to36.xise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_18to36_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_18to36_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+fifo_xlnx_512x36_2clk_18to36_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
new file mode 100644
index 000000000..9b9b1f37a
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_18to36_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_18to36_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_18to36
+}
+# ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_18to36_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_18to36
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise
new file mode 100644
index 000000000..d0c862319
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_36to18.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
new file mode 100644
index 000000000..00814f02e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
new file mode 100644
index 000000000..b3d994ae8
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating
+// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_36to18(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ empty);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [17 : 0] dout;
+output full;
+output empty;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V6_1 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(9),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(36),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(18),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(0),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(0),
+ .C_PRELOAD_REGS(1),
+ .C_PRIM_FIFO_TYPE("512x36"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(509),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(508),
+ .C_PROG_FULL_TYPE(0),
+ .C_RD_DATA_COUNT_WIDTH(10),
+ .C_RD_DEPTH(1024),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(10),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(9),
+ .C_WR_DEPTH(512),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(9),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .EMPTY(empty),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .ALMOST_FULL(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_FULL(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo
new file mode 100644
index 000000000..e93be1591
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk_36to18 YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [35 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [17 : 0]
+ .full(full),
+ .empty(empty));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_36to18.v when simulating
+// the core, fifo_xlnx_512x36_2clk_36to18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
new file mode 100644
index 000000000..d3115e7d5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Thu Aug 12 21:06:13 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_512x36_2clk_36to18
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=509
+CSET full_threshold_negate_value=508
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=18
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: a4e70980
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise
new file mode 100644
index 000000000..cfe983130
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_36to18.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_36to18.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_36to18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-08-12T14:06:16" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3646C65496E43142DA83C69469B5BF88" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt
new file mode 100644
index 000000000..54c85b15e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_512x36_2clk_36to18>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_512x36_2clk_36to18.gise
+fifo_xlnx_512x36_2clk_36to18.ngc
+fifo_xlnx_512x36_2clk_36to18.v
+fifo_xlnx_512x36_2clk_36to18.veo
+fifo_xlnx_512x36_2clk_36to18.xco
+fifo_xlnx_512x36_2clk_36to18.xise
+fifo_xlnx_512x36_2clk_36to18_flist.txt
+fifo_xlnx_512x36_2clk_36to18_readme.txt
+fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt
new file mode 100644
index 000000000..3efc586bf
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt
@@ -0,0 +1,47 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+ Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_36to18.gise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_36to18.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk_36to18.v:
+ Verilog wrapper file provided to support functional simulation.
+ This file contains simulation model customization data that is
+ passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk_36to18.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk_36to18.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_512x36_2clk_36to18.xise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_36to18_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_36to18_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+fifo_xlnx_512x36_2clk_36to18_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
new file mode 100644
index 000000000..5161c1826
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_36to18_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_36to18_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_36to18
+}
+# ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_36to18_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_36to18
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
new file mode 100644
index 000000000..9abec8c3e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
new file mode 100644
index 000000000..9cb73d5ce
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
new file mode 100644
index 000000000..6ec1e3f88
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
+// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_prog_full(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ almost_full,
+ empty,
+ prog_full);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output almost_full;
+output empty;
+output prog_full;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V6_1 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(9),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(36),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(36),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(1),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(0),
+ .C_PRELOAD_REGS(1),
+ .C_PRIM_FIFO_TYPE("512x36"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(500),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(499),
+ .C_PROG_FULL_TYPE(1),
+ .C_RD_DATA_COUNT_WIDTH(9),
+ .C_RD_DEPTH(512),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(9),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(9),
+ .C_WR_DEPTH(512),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(9),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .ALMOST_FULL(almost_full),
+ .EMPTY(empty),
+ .PROG_FULL(prog_full),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
new file mode 100644
index 000000000..64e6769d6
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk_prog_full YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [35 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [35 : 0]
+ .full(full),
+ .almost_full(almost_full),
+ .empty(empty),
+ .prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
+// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
new file mode 100644
index 000000000..f99c3c6fb
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Thu Nov 11 17:27:10 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_512x36_2clk_prog_full
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=500
+CSET full_threshold_negate_value=499
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: 6b9f6232
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
new file mode 100644
index 000000000..91dbf5819
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-11T09:27:12" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="96435AE73456681FC0EF5839C85C4C97" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
new file mode 100644
index 000000000..2eb837a3f
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_512x36_2clk_prog_full>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_512x36_2clk_prog_full.gise
+fifo_xlnx_512x36_2clk_prog_full.ngc
+fifo_xlnx_512x36_2clk_prog_full.v
+fifo_xlnx_512x36_2clk_prog_full.veo
+fifo_xlnx_512x36_2clk_prog_full.xco
+fifo_xlnx_512x36_2clk_prog_full.xise
+fifo_xlnx_512x36_2clk_prog_full_flist.txt
+fifo_xlnx_512x36_2clk_prog_full_readme.txt
+fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
new file mode 100644
index 000000000..33d50a91d
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
@@ -0,0 +1,47 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+ Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_prog_full.gise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_prog_full.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk_prog_full.v:
+ Verilog wrapper file provided to support functional simulation.
+ This file contains simulation model customization data that is
+ passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk_prog_full.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk_prog_full.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_512x36_2clk_prog_full.xise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_512x36_2clk_prog_full_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+fifo_xlnx_512x36_2clk_prog_full_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
new file mode 100644
index 000000000..e1aecccff
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full
+}
+# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-22 06:00:53 +0000