Merge branch 'fpga_next' into next

3 files changed, 149 insertions, 26 deletions

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 567feacde..6ee7ea262 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -1,5 +1,5 @@
 #
-# Copyright 2010 Ettus Research LLC
+# Copyright 2010-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -54,4 +54,5 @@ settings_bus_16LE.v \
 atr_controller16.v \
 fifo_to_wb.v \
 gpio_atr.v \
+user_settings.v \
 ))
diff --git a/fpga/usrp2/control_lib/double_buffer_tb.v b/fpga/usrp2/control_lib/double_buffer_tb.v
index a9aae6956..804e8804d 100644
--- a/fpga/usrp2/control_lib/double_buffer_tb.v
+++ b/fpga/usrp2/control_lib/double_buffer_tb.v
@@ -27,7 +27,7 @@ module double_buffer_tb();
    reg src_rdy_i = 0;
    wire dst_rdy_o;
    
-   wire dst_rdy_i = 1;
+   wire dst_rdy_i = 0;
    wire [35:0] data_o;
    reg [35:0]  data_i;
 
@@ -46,9 +46,9 @@ module double_buffer_tb();
       .data_i(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
       .data_o(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
 
-   dspengine_16to8 dspengine_16to8
+   dspengine_8to16 #(.HEADER_OFFSET(1)) dspengine_8to16
      (.clk(clk),.reset(rst),.clear(0),
-      .set_stb(set_stb), .set_addr(0), .set_data({13'h0,1'b1,18'h00400}),
+      .set_stb(set_stb), .set_addr(0), .set_data(1),
       .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
       .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
       .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
@@ -69,11 +69,13 @@ module double_buffer_tb();
 	@(posedge clk);
 	@(posedge clk);
 	@(posedge clk);
-
+/*
 	// Passthrough
 	$display("Passthrough");
 	src_rdy_i <= 1;
-	data_i <= { 2'b00,1'b0,1'b1,32'hFFFFFFFF};
+	data_i <= { 2'b00,1'b0,1'b1,32'h01234567};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'hFFFFFFFF};
 	@(posedge clk);
 	data_i <= { 2'b00,1'b0,1'b0,32'h04050607};
 	@(posedge clk);
@@ -86,16 +88,18 @@ module double_buffer_tb();
 
 	repeat (5)
 	  @(posedge clk);
-
+*/
 	$display("Enabled");
 	set_stb <= 1;
 	@(posedge clk);
 	set_stb <= 0;
-
+/*
 	@(posedge clk);
 	$display("Non-IF Data Passthrough");
 	src_rdy_i <= 1;
-	data_i <= { 2'b00,1'b0,1'b1,32'hC0000000};
+	data_i <= { 2'b00,1'b0,1'b1,32'h89acdef0};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'hC0000000};
 	@(posedge clk);
 	data_i <= { 2'b00,1'b0,1'b0,32'h14151617};
 	@(posedge clk);
@@ -111,7 +115,9 @@ module double_buffer_tb();
 	
 	$display("No StreamID, No Trailer, Even");
 	src_rdy_i <= 1;
-  	data_i <= { 2'b00,1'b0,1'b1,32'h0000FFFF};
+  	data_i <= { 2'b00,1'b0,1'b1,32'hAAAAAAAA};
+	@(posedge clk);
+  	data_i <= { 2'b00,1'b0,1'b0,32'h0000FFFF};
 	@(posedge clk);
 	data_i <= { 2'b00,1'b0,1'b0,32'h01000200};
 	@(posedge clk);
@@ -139,7 +145,9 @@ module double_buffer_tb();
 
 	$display("No StreamID, No Trailer, Odd");
 	src_rdy_i <= 1;
-  	data_i <= { 2'b00,1'b0,1'b1,32'h0000FFFF};
+  	data_i <= { 2'b00,1'b0,1'b1,32'hBBBBBBBB};
+	@(posedge clk);
+  	data_i <= { 2'b00,1'b0,1'b0,32'h0000FFFF};
 	@(posedge clk);
 	data_i <= { 2'b00,1'b0,1'b0,32'h11001200};
 	@(posedge clk);
@@ -159,30 +167,59 @@ module double_buffer_tb();
 
 	while(~dst_rdy_o)
 	  @(posedge clk);
-
+*/
+   /*
 	$display("No StreamID, Trailer, Even");
 	src_rdy_i <= 1;
-  	data_i <= { 2'b00,1'b0,1'b1,32'h0400FFFF};
+  	data_i <= { 2'b00,1'b0,1'b1,32'hCCCCCCCC};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'h21002200};
+  	data_i <= { 2'b00,1'b0,1'b0,32'h0400FFFF};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'h23002400};
+	data_i <= { 2'b00,1'b0,1'b0,32'h21222324};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'h25262728};
 	src_rdy_i <= 0;
 	@(posedge clk);
 	src_rdy_i <= 1;
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'h25002600};
+	data_i <= { 2'b00,1'b0,1'b0,32'h292a2b2c};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'h27002800};
+	data_i <= { 2'b00,1'b0,1'b0,32'h2d2e2f30};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b1,1'b0,32'h29002a00};
+	data_i <= { 2'b00,1'b1,1'b0,32'hDEADBEEF};
 	@(posedge clk);
 	src_rdy_i <= 0;
 	@(posedge clk);
-
+*/
+	while(~dst_rdy_o)
+	  @(posedge clk);
+/*
+	$display("No StreamID, Trailer, Odd");
+	src_rdy_i <= 1;
+  	data_i <= { 2'b00,1'b0,1'b1,32'hDDDDDDDD};
+	@(posedge clk);
+  	data_i <= { 2'b00,1'b0,1'b0,32'h0400FFFF};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'h21222324};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'h25262728};
+	src_rdy_i <= 0;
+	@(posedge clk);
+	src_rdy_i <= 1;
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'h292a2b2c};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'h2d2e2f30};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b1,1'b0,32'hDEBDBF0D};
+	@(posedge clk);
+	src_rdy_i <= 0;
+	@(posedge clk);
+*/
 	while(~dst_rdy_o)
 	  @(posedge clk);
 
+/*
 	$display("No StreamID, Trailer, Odd");
 	src_rdy_i <= 1;
   	data_i <= { 2'b00,1'b0,1'b1,32'h0400FFFF};
@@ -226,23 +263,45 @@ module double_buffer_tb();
 
 	while(~dst_rdy_o)
 	  @(posedge clk);
-
+*/
 	$display("StreamID, Trailer, Odd");
 	src_rdy_i <= 1;
-  	data_i <= { 2'b00,1'b0,1'b1,32'h1400FFFF};
+  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
+	@(posedge clk);
+  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};
+//	src_rdy_i <= 0;
+//	@(posedge clk);
+//	src_rdy_i <= 1;
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'ha100a200};
+	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'ha300a400};
 	src_rdy_i <= 0;
 	@(posedge clk);
 	src_rdy_i <= 1;
+  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
+	@(posedge clk);
+  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
+	@(posedge clk);
+	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};
+//	src_rdy_i <= 0;
+//	@(posedge clk);
+//	src_rdy_i <= 1;
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'ha500a600};
+	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b0,1'b0,32'ha700a800};
+	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
 	@(posedge clk);
-	data_i <= { 2'b00,1'b1,1'b0,32'hbbb0bbb0};
+	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
 	@(posedge clk);
 	src_rdy_i <= 0;
 	@(posedge clk);
diff --git a/fpga/usrp2/control_lib/user_settings.v b/fpga/usrp2/control_lib/user_settings.v
new file mode 100644
index 000000000..d87f1de21
--- /dev/null
+++ b/fpga/usrp2/control_lib/user_settings.v
@@ -0,0 +1,63 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// User settings bus
+//
+// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in
+// normal settings bus.
+//
+// Write user address to BASE
+// Write user data to BASE+1
+//
+// The user_set_stb will strobe after data write, must write new address even if same as previous one.
+
+module user_settings
+  #(parameter BASE=0)
+  (input clk,
+   input rst,
+
+   input         set_stb,
+   input [7:0]   set_addr,
+   input [31:0]  set_data,
+
+   output        set_stb_user,
+   output [7:0]  set_addr_user,
+   output [31:0] set_data_user
+   );
+
+   wire 	 addr_changed, data_changed;
+   reg 		 stb_int;
+   
+   setting_reg #(.my_addr(BASE+0),.width(8)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_addr_user),.changed(addr_changed) );
+   
+   setting_reg #(.my_addr(BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_data_user),.changed(data_changed) );
+   
+   always @(posedge clk)
+     if (rst|set_stb_user)
+       stb_int <= 0;
+     else
+       if (addr_changed)
+         stb_int <= 1;
+   
+   assign set_stb_user = stb_int & data_changed;
+   
+endmodule // user_settings
+