diff options
| author | Josh Blum <josh@joshknows.com> | 2011-08-31 18:13:02 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-31 18:13:02 -0700 |
| commit | 208885b6dc8a01a1d7095cff5b36c8451601259c (patch) | |
| tree | 264f26bf0f906580345696603adf0e5d3335194d /fpga/usrp2/control_lib | |
| parent | 92735f83fcbf27beda59bea02653bce10782bb44 (diff) | |
| parent | dfb30a5d35c4dfeac567c250b792e5d9a68e8a69 (diff) | |
| download | uhd-208885b6dc8a01a1d7095cff5b36c8451601259c.tar.gz uhd-208885b6dc8a01a1d7095cff5b36c8451601259c.tar.bz2 uhd-208885b6dc8a01a1d7095cff5b36c8451601259c.zip | |
Merge branch 'patch_release'
Diffstat (limited to 'fpga/usrp2/control_lib')
| -rw-r--r-- | fpga/usrp2/control_lib/bootram.v | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index fb7bd46c8..7821fbc4c 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -83,7 +83,7 @@ module bootram .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -93,7 +93,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB0), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -112,8 +112,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -123,7 +123,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB1), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -142,8 +142,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -153,7 +153,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB2), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -172,8 +172,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -183,7 +183,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB3), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -202,8 +202,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -213,7 +213,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB4), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -232,8 +232,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -243,7 +243,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB5), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -262,8 +262,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -273,7 +273,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB6), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input @@ -292,8 +292,8 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIA(32'hffffffff), // Port A 32-bit Data Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -303,7 +303,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB7), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input |